ADG411/ADG412/ADG413
120
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
100
OFF ISOLATION – dB
APPLICATION
80
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
OUT
follows the input signal V
IN
. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30
µV/µs.
60
40
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 7. Off Isolation vs. Frequency
110
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
100
CROSSTALK – dB
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. This compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the
±
10 V input
range. Both the acquisition and settling times are 850 ns.
+15V
+5V
2200pF
90
80
SW1
+15V
70
V
IN
AD845
–15V
1k
10k
100k
FREQUENCY – Hz
1M
10M
S
S
SW2
D
D
R
C
75
C
C
1000pF
C
H
2200pF
+15V
AD711
V
OUT
–15V
60
100
ADG411
ADG412
ADG413
Figure 8. Crosstalk vs. Frequency
–15V
Figure 9. Fast, Accurate Sample-and-Hold
–6–
REV. A
AD [ ANALOG DEVICES ]
