ADL5201
Parameter
POWER-UP INTERFACE
Power-Up Threshold
PWUP Input Bias Current
GAIN CONTROL INTERFACE
V
IH
V
IL
Maximum Input Bias Current
SPI TIMING
f
SCLK
t
DH
t
DS
t
PW
POWER INTERFACE
Supply Voltage
Quiescent Current
Test Conditions/Comments
PWUP pin
Minimum voltage to enable the device
Maximum voltage to enable the device
Min
1.4
Typ
Data Sheet
Max
Unit
V
V
μA
V
μA
MHz
ns
ns
ns
5.5
110
120
80
95
7
V
mA
mA
mA
mA
mA
3.3
1
Minimum/maximum voltage for a logic high
Maximum voltage for a logic low
LATCH, SCLK, SDIO, data pins
1/t
SCLK
Data hold time
Data setup time
SCLK high pulse width
1.4
1
20
5
5
5
4.5
3.3
0.8
Power-Down Current
High performance mode
85°C
Low power mode
85°C
PWUP low
TIMING DIAGRAMS
t
SCLK
SCLK
t
PW
t
DH
t
DS
CS
t
DS
t
DH
SDIO
DNC
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
D4
D3
D2
D1
D0
09388-002
Figure 2. SPI Interface Read/Write Mode Timing Diagram
t
DS
UPDN_DAT
UPDN_CLK
t
DS
t
PW
09388-003
UP
DN
RESET
t
DS
t
DH
Figure 3. Up/Down Mode Timing Diagram
LATCH
t
DH
Figure 4. Parallel Mode Timing Diagram
Rev. 0 | Page 4 of 28
09388-104
A5 TO A0
AD [ ANALOG DEVICES ]
