ADM1032–SPECIFICATIONS
(T = T
A
MIN
to T
MAX
, V
DD
= V
MIN
to V
MAX
, unless otherwise noted.)
Max
5.5
215
10
2.8
2.4
±
3
±
1
±
3
Unit
V
µA
µA
V
V
°C
°C
°C
°C
°C
µA
µA
ms
Test Conditions/Comments
Parameter
POWER SUPPLY
Supply Voltage, V
DD
Average Operating Supply Current, I
CC
Undervoltage Lockout Threshold
Power-On Reset Threshold
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
Resolution
Remote Diode Sensor Accuracy
Resolution
Remote Sensor Source Current
Conversion Time
Min
3.0
Typ
3.30
170
5.5
2.55
2.35
1
0.0625 Conversions/Sec Rate
1
Standby Mode
V
DD
Input, Disables ADC, Rising Edge
±
1
1
0
≤
T
A
≤
100°C, V
CC
= 3 V to 3.6 V
60°C
≤
T
D
≤
100°C, V
CC
= 3 V to 3.6 V
0°C
≤
T
D
≤
120°C
High Level, Note 2
Low Level, Note 2
From Stop Bit to Conversion Complete
(Both Channels) One-Shot Mode with
Averaging Switched On
One-Shot Mode with Averaging Off
(i.e., Conversion Rate = 32 or 64
Conversions per Second)
0.125
230
13
35.7
142.8
5.7
22.8
ms
OPEN-DRAIN DIGITAL OUTPUTS
(THERM,
ALERT)
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
SMBus INTERFACE
2
Logic Input High Voltage, V
IH
SCLK, SDATA
Logic Input Low Voltage, V
IL
Hysteresis
SCLK, SDATA
SMBus Output Low Sink Current
ALERT
Output Low Sink Current
Logic Input Current, I
IH
, I
IL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Timeout
SMBus Clock Low Time, t
LOW
SMBus Clock High Time, t
HIGH
SMBus Start Condition Setup Time, t
SU:STA
SMBus Start Condition Hold Time, t
HD:STA
SMBus Stop Condition Setup Time, t
SU:STO
SMBus Data Valid to SCLK Rising Edge
Time, t
SU:DAT
SMBus Data Hold Time, t
HD:DAT
SMBus Bus Free Time, t
BUF
SCLK Falling Edge to SDATA
Valid Time, t
VD,DAT
SCLK, SDATA Rise Time, t
R
SCLK, SDATA Fall Time, t
F
2.1
0.1
0.4
1
V
µA
V
I
OUT
= –6.0 mA
2
V
OUT
= V
DD2
V
DD
= 3 V to 5.5 V
V
DD
= 3 V to 5.5 V
SDATA Forced to 0.6 V
ALERT
Forced to 0.4 V
0.8
500
6
1
–1
5
25
4.7
4
4.7
4
4
250
300
4.7
1
1
300
100
64
V
mV
mA
mA
µA
pF
kHz
ms
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
+1
Note 3
t
LOW
between 10% Points
t
HIGH
between 90% Points
Time from 10% of SDATA to 90%
of SCLK
Time from 90% of SCLK to 10%
of SDATA
Time for 10% or 90% of SDATA to
10% of SCLK
Between Start/Stop Condition
Master Clocking in Data
NOTES
1
See Table VI for information on other conversion rates.
2
Guaranteed by Design, not production tested.
3
The SMBus timeout is a programmable feature. By default it is not enabled. Details on how to enable it are available in the SMBus section of this data sheet.
Specifications subject to change without notice.
–2–
REV. 0
AD [ ANALOG DEVICES ]
