a
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics, and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch, and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
ADSP-2106x SHARC
®
DSP Microcomputer Family
ADSP-21060/ADSP-21060L
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced MQFP Package
225 PBGA Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel
with Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
4 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
DUAL-PORTED SRAM
BLOCK 0
BLOCK 1
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32
48-BIT
ADDR
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
DATA
DATA
JTAG
TEST &
EMULATION
7
I/O PORT
DATA
DATA
ADDR
ADDR
DAG1
8
4
32
8
DAG2
4
24
PROGRAM
SEQUENCER
24
32
IOD
48
IOA
17
PM ADDRESS BUS
DM ADDRESS BUS
EXTERNAL
PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
32
PM DATA BUS
BUS
CONNECT
(PX)
DM DATA BUS
48
40/32
DATA BUS
MUX
HOST PORT
48
DATA
REGISTER
FILE
MULTIPLIER
16
40-BIT
IOP
REGISTERS
(MEMORY MAPPED)
DMA
CONTROLLER
SERIAL PORTS
(2)
4
6
6
36
BARREL
SHIFTER
ALU
CONTROL,
STATUS &
DATA BUFFERS
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD [ ANALOG DEVICES ]
