a
KEY FEATURES
Up to 600 MHz, 1.67 ns instruction cycle rate
24M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid
array package
Dual-computation blocks—each containing an ALU, a
multiplier, a shifter, a register file, and a communications
logic unit (CLU)
Dual-integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, four link ports, SDRAM controller, programmable
flag pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
DATA ADDRESS GENERATION
INTEGER
J ALU
PROGRAM
SEQUENCER
ADDR
FETCH
32-BIT × 32-BIT
J-BUS ADDR
J-BUS DATA
K-BUS ADDR
BTB
K-BUS DATA
I-BUS ADDR
PC
I-BUS DATA
32
32
INTEGER
K ALU
32-BIT × 32-BIT
32
128
32
128
32
128
S-BUS ADDR
S-BUS DATA 128
21
•
TigerSHARC
®
Embedded Processor
ADSP-TS201S
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for telecommunications
infrastructure and other large, demanding multiprocessor
DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other
(multiprocessor) DSPs
Eases DSP programming through extremely flexible instruc-
tion set and high-level-language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Provides on-chip arbitration for glueless multiprocessing
24M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4 × CROSSBAR CONNECT
A
D
A
D
A
D
A
D
SOC BUS
JTAG
JTAG PORT
6
EXTERNAL
PORT
32
ADDR
HOST
MULTI-
PROC
SDRAM
CTRL
C-BUS
ARB
64
DATA
8
CTRL
10
CTRL
SOC
I/F
DMA
EXT DMA
REQ 4
IAB
T
128
SHIFT
X
REGISTER
128
ALU MUL
FILE
32-BIT × 32-BIT
128
128
DAB
DAB
COMPUTATIONAL BLOCKS
CLU
Y
REGISTER
MUL ALU
FILE
32-BIT × 32-BIT
SHIFT
CLU
LINK PORTS
4
8
IN
L0
4
OUT 8
4
8
IN
L1
4
OUT 8
4
8
IN
L2
4
OUT 8
4
8
IN
L3
4
OUT 8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
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©2006
Analog Devices, Inc. All rights reserved.
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