ADV7170/ADV7171
5 V TIMING SPECIFICATIONS
Parameter
MPU PORT
3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
ANALOG OUTPUTS
3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND
PIXEL PORT
5, 6
f
CLOCK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Digital Output Access Time, t
13
Digital Output Hold Time, t
144
Pipeline Delay, t
15 4
TELETEXT
3, 4, 7
Digital Output Access Time, t
16
Data Setup Time, t
17
Data Hold Time, t
18
RESET CONTROL
3, 4
RESET
Low Time
6
(V
AA
= 4.75 V – 5.25 V
1
, V
REF
= 1.235 V, R
SET
= 150
otherwise noted.)
. All specifications T
MIN
to T
MAX2
unless
Min
0
0.6
1.3
0.6
0.6
100
Typ
Max
400
Units
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
7
0
27
8
8
3.5
4
4
3
11
8
48
20
2
6
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
2
Temperature range T
MIN
to T
MAX
: 0
o
C to +70
o
C.
3
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load
≤
10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC,
FIELD/VSYNC,
BLANK
Clock Input:
CLOCK
7
Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
REV. 0
–5–
AD [ ANALOG DEVICES ]
