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EVAL-ADCMP551BRQZ 参数 Datasheet PDF下载

EVAL-ADCMP551BRQZ图片预览
型号: EVAL-ADCMP551BRQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 单电源高速PECL / LVPECL比较 [Single Supply High Speed PECL/LVPECL Comparators]
分类和应用:
文件页数/大小: 16 页 / 259 K
品牌: AD [ ANALOG DEVICES ]
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Data Sheet
FEATURES
Single power supply
500 ps propagation delay input to output
125 ps overdrive dispersion
Differential PECL/LVPECL compatible outputs
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
700 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable hysteresis
Single Supply High Speed
PECL/LVPECL Comparators
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
Q OUTPUT
INVERTING
INPUT
ADCMP551/
ADCMP552/
ADCMP553
Q OUTPUT
*ADCMP552 ONLY
Figure 1.
GENERAL DESCRIPTION
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
The ADCMP551/ADCMP552/ADCMP553 are single supply,
high speed comparators fabricated on Analog Devices’ proprietary
XFCB process. The devices feature a 500 ps propagation delay
with less than 125 ps overdrive dispersion. Overdrive dispersion,
a measure of the difference in propagation delay under differing
overdrive conditions, is a particularly important characteristic
of high speed comparators. A separate programmable hysteresis
pin is available on the ADCMP552.
A differential input stage permits consistent propagation delay
with a common-mode range from –0.2 V to VCCI – 2.0 V. Outputs
are complementary digital signals and are fully compatible with
PECL and 3.3V LVPECL logic families. The outputs provide
sufficient drive current to directly drive transmission lines
terminated in 50 Ω to VCCO − 2 V. A latch input is included
and permits tracking, track-and-hold, or sample-and-hold
modes of operation. The latch input pins contain internal pull-
ups that set the latch in tracking mode when left open.
The ADCMP551/ADCMP552/ADCMP553 are specified over
the –40°C to +85°C industrial temperature range. The ADCMP551
is available in a 16-lead QSOP package; the ADCMP552 is available
in a 20-lead QSOP package; and the ADCMP553 is available in
an 8-lead MSOP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
04722-001
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT