Data Sheet
ADuC7024/ADuC7025
ADuC7019/20/21/22/24/25/26/27/28/29
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
DACV
DD
AV
DD
AGND
DACGND
DAC
REF
V
REF
P4.5/PLAO[13]
P4.4/PLAO[12]
P4.3/PLAO[11]
P4.2/PLAO[10]
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
GND
REF
ADCNEG
DAC0/ADC12
DAC1/ADC13
TMS
TDI
P4.6/PLAO[14]
P4.7/PLAO[15]
BM/P0.0/CMP
OUT
/PLAI[7]
P0.6/T1/MRST/PLAO[3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
ADuC7024/
ADuC7025
TOP VIEW
(Not to Scale)
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P4.1/PLAO[9]
P4.0/PLAO[8]
IOV
DD
IOGND
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
P3.7/PWM
SYNC
/PLAI[15]
P3.6/PWM
TRIP
/PLAI[14]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONV
START
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P3.0/PWM0
H
/PLAI[8]
P3.1/PWM0
L
/PLAI[9]
P3.2/PWM1
H
/PLAI[10]
P3.3/PWM1
L
/PLAI[11]
P0.3/TRST/ADC
BUSY
RST
P3.4/PWM2
H
/PLAI[12]
P3.5/PWM2
L
/PLAI[13]
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED FOR MECHANICAL PURPOSES AND LEFT UNCONNECTED.
Figure 23. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
DACV
DD
AV
DD
AGND
DACGND
DAC
REF
V
REF
P4.5/PLAO[13]
P4.4/PLAO[12]
P4.3/PLAO[11]
P4.2/PLAO[10]
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
GND
REF
ADCNEG
DAC0/ADC12
DAC1/ADC13
TMS
TDI
P4.6/PLAO[14]
P4.7/PLAO[15]
BM/P0.0/CMP
OUT
/PLAI[7]
P0.6/T1/MRST/PLAO[3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
ADuC7024/
ADuC7025
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P4.1/PLAO[9]
P4.0/PLAO[8]
IOV
DD
IOGND
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
P3.7/PWM
SYNC
/PLAI[15]
P3.6/PWM
TRIP
/PLAI[14]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONV
START
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P3.0/PWM0
H
/PLAI[8]
P3.1/PWM0
L
/PLAI[9]
P3.2/PWM1
H
/PLAI[10]
P3.3/PWM1
L
/PLAI[11]
P0.3/TRST/ADC
BUSY
RST
P3.4/PWM2
H
/PLAI[12]
P3.5/PWM2
L
/PLAI[13]
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
04955-067
04955-068
Figure 24. 64-Lead LQFP Pin Configuration (ADuC7024/ADuC7025)
Rev. F | Page 25 of 104
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