ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 80.
Table 78. GPIO Pin Function Descriptions
Configuration
Port Pin
00
01
10
11
Table 80. GPxCON MMR Bit Descriptions
0
1
2
P0.0 GPIO
P0.1 GPIO
P0.2 GPIO
P0.3 GPIO
P0.4 GPIO/IRQ0 PWMTRIP
P0.5 GPIO/IRQ1 ADCBUSY
P0.6 GPIO/T1
P0.7 GPIO
P1.0 GPIO/T1
P1.1 GPIO
P1.2 GPIO
P1.3 GPIO
CMP
MS0
BLE
BHE
A16
MS1
MS2
PLAI[7]
Bit
Description
PWM2H
PWM2L
TRST
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
Reserved.
Select function of the Px.7 pin.
Reserved.
Select function of the Px.6 pin.
Reserved.
Select function of the Px.5 pin.
Reserved.
Select function of the Px.4 pin.
Reserved.
Select function of the Px.3 pin.
Reserved.
Select function of the Px.2 pin.
Reserved.
ADCBUSY
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
MRST
ECLK/XCLK1
SIN
SOUT
RTS
SIN
SCL0
SDA0
SCL1
SDA1
SCLK
MISO
MOSI
CS
CTS
P1.4 GPIO/IRQ2 RI
P1.5 GPIO/IRQ3 DCD
P1.6 GPIO
P1.7 GPIO
7:6
DSR
DTR
5:4
3:2
Select function of the Px.1 pin.
Reserved.
2
1:0
Select function of the Px.0 pin.
P2.0 GPIO
P2.1 GPIO
P2.2 GPIO
P2.3 GPIO
P2.4 GPIO
P2.5 GPIO
P2.6 GPIO
P2.7 GPIO
P3.0 GPIO
P3.1 GPIO
P3.2 GPIO
P3.3 GPIO
P3.4 GPIO
P3.5 GPIO
P3.6 GPIO
P3.7 GPIO
P4.0 GPIO
P4.1 GPIO
P4.2 GPIO
P4.3 GPIO
P4.4 GPIO
P4.5 GPIO
P4.6 GPIO
P4.7 GPIO
CONVSTART
PWM0H
PWM0L
SOUT
WS
PLAO[5]
PLAO[6]
PLAO[7]
Table 81. GPxPAR Registers
RS
Name
Address
Default Value
0x20000000
0x00000000
Access
R/W
AE
GP0PAR
GP1PAR
0xFFFFF42C
0xFFFFF43C
PWM0H
PWM0L
PWM1H
PWM1L
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
PWMTRIP
PWMSYNC
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
R/W
GPxPAR program the parameters for Port 0 and Port 1. Note that
the GPxDAT MMR must always be written after changing the
GPxPAR MMR.
3
PLAI[8]
PLAI[9]
Table 82. GPxPAR MMR Bit Descriptions
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
Bit
Description
31
Reserved.
30:29
28
27
Drive strength Px.7.
Pull-Up Disable Px.7.
Reserved.
26:25
24
23
Drive strength Px.6.
Pull-Up Disable Px.6.
Reserved.
4
22:21
20
19
Drive strength Px.5.
Pull-Up Disable Px.5.
Reserved.
18:17
16
15
Drive strength Px.4.
Pull-Up Disable Px.4.
Reserved.
14:13
12
11
Drive strength Px.3.
Pull-Up Disable Px.3.
Reserved.
1 When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
2
CONVSTART signal is active in all modes of P2.0.
The
10:9
8
7
Drive strength Px.2.
Pull-Up Disable Px.2.
Reserved.
Table 79. GPxCON Registers
Name
Address
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Access
R/W
R/W
R/W
R/W
6:5
4
3
Drive strength Px.1.
Pull-Up Disable Px.1.
Reserved.
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
2:1
0
Drive strength Px.0.
Pull-Up Disable Px.0.
R/W
Rev. F | Page 68 of 104
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