Data Sheet
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AV
DD
and IOV
DD
, respectively) allow
AV
DD
to be kept relatively free of noisy digital signals often
present on the system IOV
DD
line. In this mode, the part can
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can
be designed to operate with an IOV
DD
voltage level of 3.3 V
whereas the AV
DD
level can be at 3 V or vice versa. A typical
split supply configuration is shown in Figure 87.
DIGITAL
SUPPLY
+
–
10µF
10µF
ANALOG
SUPPLY
+
–
ADuC7019/20/21/22/24/25/26/27/28/29
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
IOV
DD
Supply Sensitivity
The IOV
DD
supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOV
DD
, a filter such as the one shown in Figure 89
is recommended.
1µH
ADuC7026
AV
DD
26
54
73
74
IOV
DD
DACV
DD 75
GND
REF 8
DACGND
70
0.1µF
0.1µF
ADuC7026
26
54
25
53
AGND
71
04955-044
IOGND
REFGND
67
DIGITAL +
SUPPLY –
10µF
IOV
DD
Figure 87. External Dual Supply Connections
0.1µF
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
DD
by placing a small series resistor
and/or ferrite bead between AV
DD
and IOV
DD
and then decoupling
AV
DD
separately to ground. An example of this configuration is
shown in Figure 88. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AV
DD
supply line as well.
DIGITAL SUPPLY
+ 10µF
–
BEAD
1.6Ω
10µF
IOGND
53
Figure 89. Recommended IOV
DD
Supply Filter
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOV
DD
for the
core logic. The LV
DD
pin is the 2.6 V supply for the core logic.
An external compensation capacitor of 0.47
µF
must be
connected between LV
DD
and DGND (as close as possible to
these pins) to act as a tank of charge as shown in Figure 90.
ADuC7026
27
ADuC7026
AV
DD
26
54
73
74
IOV
DD
DACV
DD 75
GND
REF 8
DACGND
70
0.1µF
0.1µF
25
53
AGND
71
REFGND
67
04955-045
IOGND
LV
DD
DGND
0.47mF
28
Figure 88. External Single Supply Connections
Note that in both Figure 87 and Figure 88, a large value (10 µF)
reservoir capacitor sits on IOV
DD
, and a separate 10 µF capacitor
sits on AV
DD
. In addition, local small-value (0.1 µF) capacitors are
located at each AV
DD
and IOV
DD
pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AV
DD
pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Figure 90. Voltage Regulator Connections
The LV
DD
pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOV
DD
to help improve line regulation performance of the on-
chip voltage regulator.
Rev. F | Page 93 of 104
04955-046
04955-087
25
AD [ ANALOG DEVICES ]
