11 mW Power, 2.3 V to 5.5 V,
Complete DDS
AD9838
FEATURES
2.3 V to 5.5 V power supply
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
Output frequency up to 8 MHz
Sinusoidal and triangular outputs
On-board comparator
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
11 mW power consumption at 2.3 V
20-lead LFCSP
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits wide: with a 16 MHz
clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz
clock rate, the AD9838 can be tuned to 0.02 Hz resolution.
Frequency and phase modulation are configured by loading
registers through the serial interface and by toggling the registers
using software or the FSELECT and PSELECT pins, respectively.
The AD9838 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The
analog and digital sections are independent and can be run from
different power supplies; for example, AVDD can equal 5 V with
DVDD equal to 3 V.
The AD9838 has a power-down pin (SLEEP) that allows external
control of the power-down mode. Sections of the device that are
not being used can be powered down to minimize current con-
sumption. For example, the DAC can be powered down when
a clock output is being generated.
The AD9838 is available in a 20-lead LFCSP_WQ package.
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Test and medical equipment
GENERAL DESCRIPTION
The
is a low power DDS device capable of producing high
performance sine and triangular outputs. It also has an on-board
comparator that allows a square wave to be produced for clock
generation. Consuming only 11 mW of power at 2.3 V, the
AD9838 is an ideal candidate for power-sensitive applications.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DGND
DVDD
CAP/2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
REFOUT
FSADJUST
REGULATOR
VCC
2.5V
28-BIT FREQ0
REG
MUX
28-BIT FREQ1
REG
MCLK
FSELECT
PHASE
ACCUMULATOR
(28-BIT)
Σ
12
SIN
ROM
MUX
10-BIT
DAC
IOUT
IOUTB
MSB
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDE
BY 2
16-BIT CONTROL
REGISTER
SERIAL INTERFACE
AND
CONTROL LOGIC
MUX
SIGN BIT OUT
COMPARATOR
VIN
AD9838
FSYNC
SCLK
SDATA
PSELECT
SLEEP RESET
09077-001
Figure 1.
Rev. A
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