Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Features
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Applications
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2.2 GHz operational
Dual-band optimized
Low supply current (5.1 mA)
Surface-mount 14-pin TSSOP package
Scaled PD gain for dual-band operation
Programmable phase-detector polarity
Synchronous or forced counter update loading
Powerdown mode via external pin or serial bus
Low-load capacitance on reference input buffer
GSM900/1800/1900
North American IS-136/137
Personal Digital Cellular (Japan RCR-27)
Personal Handy Phone (Japan RCR-28)
CDMA (IS-95)
LD
REF_IN
R
11-BIT COUNTER
TCXO
IPD SETTING
PD POLARITY
IREF
M
11-BIT COUNTER
PHASE
DETECTOR
V
DDC
V
CP
VCO BAND A
VCO BAND B
PRESCALER
÷64/65
A
7-BIT COUNTER
MAIN_IN
IREF
HIGH-PRECISION
CURRENT
REFERENCE
RREF
V
DDC
OFF CHIP
IPD SETTING
PD POLARITY
BAND
CONTROL
LOGIC
24-BIT SERIAL
SHIFT REGISTER
LAT
DAT
CLK
Figure 1. Block Diagram with Pinout
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