3
C10
100nF
100uF
MAX1722
VDD
MVDD
IRQ
11
10
Q2
MMBT3904
PTC0
RST
20
C19
10nF
R18
27
C19
47nF
R21
Open
C12
47pF
MC68HC908QY4
R26
1M
8
C8
16
15
4
PTA1
PTB2
VSS
PTA0
100nF
ADNS-3040
R22
10K
MC68HC908JB12
6
U3
BAT+1
C11
100uF
L1
22uH
LX
5
R8
10
MVDD
VDD
R10
10
AVDD
R11
10
LVDD
R12
10
R9
10
OUT
4 C9
VDDA
1
2
FB
GND
BATT
BAT-1
R6 R7
1M 1.1M
3
2
3
1
LB
U2
8
14
11
6
PTB6
PTA2
PTB0
3
R3
100K
PTB5
VDD
7
13
10
PTA5
PTA4
PTA3
PTB7
PTB4
PTB3
1
2
3
4
5
10
U1
NCS
MISO
MB
1
VDD
2
3
15 C1
1uF
GND
VDD
C2
10nF
16
SCLK
GND
U4
C17
30pF
2
1
RB
12
9
13
MOSI
GND
USB BUS
OSC1
2
VDD
Z2
VREG
Z-Wheel
R25
X1
10M 12MHz
C18
30pF
R4
Open
5
G2
Z1
G1
C14
OSC2
3
VDDA
R27
1M
R1
0
4
2
R2
100K
3
2
PTB1
4
GND
C13
47uF
100nF
L2
R20
1K5
12
MOTION
AVDD
D+
PTE3
AVDD
11 C3
1uF
SHTDWN
AGND
NC
AGDN
R17
27
R19
Open
C 11
47pF
8
C4
10nF
19
14
17
18
1
20
NC
AGND
D-
9 PTE4
L3
5
C7
10uF
D1
9 HLMP-ED80
NC
XY_LED
5 VDD
C16
C14
6
NC
LED_GND
LVDD
C5
1uF
7
VDDA
RF_OFF
RF_DATA
MVDD
ID
Button
R5
1M
C6
10nF
C15
47uF
100nF
C13
47uF
100nF
Q1
MMBT3906
PTE1
7 RF_DATA
VDDA
RF_OFF
PTA4
R23
10K
15
R24
10
1
VSS
RF
Receiver
Circuitry
RF
Transmitter
Circuitry
Notes The supply and ground paths should be laid out using a star topology.
Figure 8. Schematic Diagram for Interface between ADNS-3040 and microcontroller
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
