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HCPL-073L 参数 Datasheet PDF下载

HCPL-073L图片预览
型号: HCPL-073L
PDF下载: 下载PDF文件 查看货源
内容描述: 低输入电流,高增益LVTTL / LVCMOS兼容3.3 V光电耦合器 [Low Input Current High Gain LVTTL/LVCMOS Compatible 3.3 V Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 13 页 / 190 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Agilent HCPL-270L/ 070L/273L/073L
Low Input Current High Gain
LVTTL/LVCMOS Compatible
3.3 V Optocouplers
Data Sheet
Features
• Low power consumption
• High current transfer ratio
• Low input current requirements –
0.5 mA
Description
These high gain series couplers use
a Light Emitting Diode and an
integrated high gain photodetector
to provide extremely high current
transfer ratio between input and
output. Separate pins for the
photodiode and output stage result
in LVTTL compatible saturation
voltages and high speed operation.
Where desired, the V
CC
and V
O
terminals may be tied together to
achieve conventional photo-
Functional Diagram
darlington operation. A base
access terminal allows a gain
bandwidth adjustment to be
made.
These optocouplers are for use in
LVTTL/LVCMOS or other low
power applications. A 400%
minimum current transfer ratio is
guaranteed over 0 to +70˚C
operating range for only 0.5 mA
of LED current.
• LVTTL/LVCMOS compatible output
• Performance guaranteed over
temperature 0˚C to +70˚C
• Base access allows gain
bandwidth adjustment
• High output current – 60 mA
• Safety approval, UL, VDE, CSA
(pending)
Applications
• Ground isolate most logic
families – LVTTL/LVCMOS
• Low input current line receiver
• High voltage insulation
• EIA RS-232C line receiver
HCPL-270L/070L
NC 1
ANODE 2
CATHODE 3
NC 4
8 V
CC
7 V
B
6 V
O
5 GND
ANODE
1
1
CATHODE
1
2
CATHODE
2
3
ANODE
2
4
SHIELD
TRUTH TABLE
LED
V
O
ON
LOW
OFF
HIGH
HCPL-273L/073L
8 V
CC
7 V
O1
6 V
O2
5 GND
• Telephone ring detector
• 117 V AC line voltage status
indicator – low input power
dissipation
• Low power systems – ground
isolation
A 0.1
µF
bypass capacitor connected between pins 8 and 5 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.