7
Notes:
1. Derate linearly above 55
°C
free air
temperature at a rate of 3.8 mW/
°C.
Proper application of the derating
factors will prevent IC junction
temperatures from exceeding 125
°C
for ambient temperatures up to 85
°C.
2. Derate linearly above a free-air
temperature of 70
°C
at a rate of 2.3
mW/
°C.
A significant amount of
power may be dissipated in the
HCPL-4100 output circuit during the
transition from the SPACE state to
the MARK state when driving a data
line or capacitive load (C
OUT
). The
average power dissipation during the
transition can be estimated from the
following equation which assumes a
linear discharge of a capacitive load:
P = I
SC
(V
SO
+ V
MO
)/2, where V
SO
is
the output voltage in the SPACE
state. The duration of this transition
can be estimated as t = C
OUT
(V
SO
-
V
MO
)/I
SC
. For typical applications
driving twisted pair data lines with
NRZ data as shown in Figure 11, the
transition time will be less than 10%
of one bit time.
3. Derate linearly above 55
°C
free-air
temperature at a rate of 5.1 mW/
°C.
4. The maximum current that will flow
into the output in the mark state (I
SC
)
is internally limited to protect the
device. The duration of the output
short circuit shall not exceed 10 ms.
5. The device is considered a two
terminal device, pins 1, 2, 3, and 4
are connected together, and pins 5,
6, 7, and 8 are connected together.
6. The t
PLH
propagation delay is
measured from the 1.3 volt level on
the leading edge of the input pulse to
the 10 mA level on the leading edge
of the output pulse.
7. The t
PHL
propagation delay is
measured from the 1.3 volt level on
the trailing edge of the input pulse to
the 10 mA level on the trailing edge
of the output pulse.
8. The rise time, t
r
, is measured from the
10% to the 90% level on the rising
edge of the output current pulse.
9. The fall time, t
f
, is measured from the
90% to the 10% level on the falling
edge of the output current pulse.
10. Common mode transient immunity in
the logic high level is the maximum
(positive) dV
CM
/dt on the leading
edge of the common mode pulse,
V
CM
, that can be sustained with the
output in a Mark ("H") state (i.e.,
I
O
> 12 mA).
11. Common mode transient immunity in
the logic low level is the maximum
(positive) dV
CM
/dt on the leading
edge of the common mode pulse,
V
CM
, that can be sustained with the
output in a Space ("L") state (i.e., I
O
< 3 mA).
12. Use of a 0.1
µF
bypass capacitor
connected between pins 5 and 8 is
recommended.
13. In accordance with UL 1577, each
optocoupler is momentary withstand
proof tested by applying an insulation
test voltage
≥
3000 V rms for 1
second (leakage detection current
limit, I
i-o
≤
5
µA).
3.0
2.8
V
O
– OUTPUT VOLTAGE – V
3.5
2.6
2.4
V
O
– OUTPUT VOLTAGE – V
2.5
2.0
1.5
1.0
0.5
0
V
CC
= 5 V
V
I
= 2 V
T
A
= 25 °C
I
S
– SPACE CURRENT – mA
I
O
20 mA
V
CC
= 5 V
V
I
= 2 V
1.3
3.0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
20 V
V
CC
= 5 V
V
I
= 0.8 V
12 mA
2.2
2.0
1.8
1.6
1.4
1.2
-40
-20
0
20
40
60
80
100
T
A
– TEMPERATURE – °C
2 mA
V
O
27 V
0
5
10
15
20
25
30
-40
-20
0
20
40
60
80
100
I
O
– OUTPUT CURRENT – mA
T
A
– TEMPERATURE – °C
Figure 2. Typical Mark State Output
Voltage vs. Temperature.
Figure 3. Typical Output Voltage vs.
Loop Current.
Figure 4. Typical Space State Output
Current vs. Temperature.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
