Inhibit Logic
The Inhibit Logic Section samples
the OE and SEL signals on the
falling edge of the clock and, in
response to certain conditions
(see Figure 10 below), inhibits
the position data latch. The RST
signal asynchronously clears the
inhibit logic, enabling the latch. A
simplified logic diagram of the
inhibit circuitry is illustrated in
Figure 11.
output and whether or not the
output bus is in the high-Z state.
In the case of the HCTL-2000 the
data latch is only 12 bits wide
and the upper four bits of the
high byte are internally set to
zero.
Bus Interface
The bus interface section consists
of a 16 to 8 line multiplexer and
an 8-bit, three-state output
buffer. The multiplexer allows
independent access to the low
and high bytes of the position
data latch. The SEL and OE
signals determine which byte is
Inhibit
Signal
1
1
0
The quadrature decoder output
section consists of count and up/
down outputs derived from the
4X decode logic of the HCTL-
2020. When the decoder has
detected a count, a pulse, one-
half clock cycle long, will be
output on the CNT
DCDR
pin. This
output will occur during the clock
cycle in which the internal
counter is updated. The U/D pin
Cascade Output (HCTL-
2020 Only)
The cascade output also consists
of count and up/down outputs.
When the HCTL-2020 internal
counter overflows or underflows,
a pulse, one-half clock cycle long,
will be output on the CNT
CAS
pin.
This output will occur during the
clock cycle in which the internal
counter is updated. The U/D pin
will be set to the proper voltage
level one clock cycle before the
rising edge of the CNT
CAS
pulse,
and held one clock cycle after the
rising edge of the CNT
CAS
pulse.
These outputs are not affected by
the inhibit logic. See Figures 5
and 12 for detailed timing.
Step SEL
1
2
3
L
H
X
OE CLK
L
L
H
Action
Set inhibit; read high byte
Read low byte; starts reset
Completes inhibit logic reset
Figure 10. Two Byte Read Sequence.
Figure 11. Simplified Inhibit Logic.
2-187
MOTION SENSING
AND CONTROL
Quadrature Decoder
Output (HCTL-2020
Only)
will be set to the proper voltage
level one clock cycle before the
rising edge of the CNT
DCDR
pulse, and held one clock cycle
after the rising edge of the
CNT
DCDR
pulse. These outputs
are not affected by the inhibit
logic. See Figures 5 and 12 for
detailed timing.
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
