Functional Pin Description
Table 4. Functional Pin Descriptions.
Pin
Symbol
HCTL
2032/
2032-SC
1
18
5
15
16
14
13
17
19
12
11
HCTL
2022
1
12
3
10
NC
9
NC
11
NC
8
NC
Description
V
DD
V
SS
CLK
CHA
X
CHA
Y
CHB
X
CHB
Y
CHI
X
CHI
Y
RSTNX
RSTNY
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA
X
, CHA
Y
, CHB
X
, and CHB
Y
are Schmitt-trigger inputs that accept the outputs from
a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHA
X
and CHB
X
are the 1
st
axis and CHA
Y
and CHB
Y
are the 2
nd
axis.
CHI
X
and CHI
Y
are Schmitt-trigger inputs that accept the outputs of Index channel
from an incremental optical shaft encoder.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST
X
/ and RST
Y
/ are asynchronous with
respect to any other input signals. RST
X
/ is to reset the 1
st
axis counter and RST
Y
/ is
to reset the 2
nd
axis counter.
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL
1
and SEL
2
also
control the internal inhibit logic.
OEN
7
5
SEL1
SEL2
6
26
4
17
SEL1
0
1
0
1
EN1
EN2
2
3
NC
NC
SEL2
1
1
0
0
MSB
D4
BYTE SELECTED
2ND
3RD
D3
D2
LSB
D1
These CMOS control pins are set to high or low to activate the selected count mode
before the decoding begins.
EN1
0
1
0
1
EN2
0
0
1
1
4x
On
On
On
Count Modes
2x
Illegal Mode
1x
X/Y
CNTDEC
X
CNTDEC
Y
U/Dx
U/Dy
32
27
28
8
9
NC
NC
NC
6
NC
Select the 1
st
or 2
nd
axis data to be read. Low bit enables the 1
st
axis data, while high
bit enables the 2
nd
axis data.
A pulse is presented on this LSTTL-compatible output when the quadrature decoder
(4x/2x/1x) has detected a state transition. CNTDEC
X
is for 1
st
axis and CNTDEC
Y
is
for 2
nd
axis.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDEC and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before the
rising edge of the CNTDEC and CNTCAS outputs.
5
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