AIC1650
PIN DESCRIPTIONS
PIN 1: VIN
- 4V to 20V input supply voltage.
PIN 2: VREF - 1.22V reference output. Bypass
with a 0.047
µ
F capacitor to GND.
Sourcing capability is guaran-
teed to be greater than 250
µ
A.
PIN 3: SHDN- Logic input to shutdown the chip.
>1.5V = normal operation,
GND = shutdown
In shutdown mode DLOW and
DHI pins are at high level.
PIN 4: FB
- Feedback signal input to sense
ground. Connecting a resistor
R1 to V
OUT
and a resistor R2 to
V
REF
pin yields the output volt-
age:
V
OUT
= -(R1/R2 ) x V
REF
PIN 5: GND - Power ground.
PIN 6: DLOW - Driver sinking output. Connected
to DHI when using an external
P-channel MOSFET. When us-
ing an external PNP bipolar
transistor, connect a resistor RB
from this pin to DHI. RB value
depends on V
IN
, inductor and
PNP bipolar transistor. By ad-
justing the RB value, efficiency
can be optimized.
PIN 7: DHI
- Driver sourcing output. Connect
to gate of the external P-channel
MOSFET or base of the PNP bi-
polar transistor.
- Current-limit input. This pin
clamps the switch peak current
to prevent over-current damage
to the external switch.
PIN 8: CL
APPLICATION INFORMATIONS
Max. Output Power vs V
IN
1.8
1.6
1.4
The typical application circuit generates an adjustable
negative voltage for contrast bias of LCD displays.
Efficiency and output power can be optimized by us-
ing appropriate inductor and switch. The following
formulas provide a guideline for determining the op-
timal component values:
L
=
(11.1
−
0.15
×
V
IN
)
×
Typical Application Circuit
100µH
120µH
150µH
Max. Output Power (W)
1.2
1
0.8
0.6
0.4
0.2
0
180µH
220µH
270µH
300µH
330µH
V
IN
I
OUT
×
V
OUT
Inductor Value
4
6
8
10
12
14
16
18
20
PNP :
V
CEO
>
V
IN
+
V
OUT
I
C,MAX
≥
200
×
V
CE
<
0. 4V at I
and
β
=
10
I
OUT
V
IN
C
V
IN
(V)
= 200
×
I
OUT
V
IN
RB
≅
3 x L x (V
IN
- 0.8)
where, units: V
IN
& V
OUT
in V, I
OUT
in A, L in
µH,
RB in
Ω
4
AIC [ ANALOG INTERGRATIONS CORPORATION ]
