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Device Configuration
Device Configuration
The EPC1, EPC2, and EPC1441 devices store configuration data in its erasable
programmable read-only memory (EPROM) array and serially clock data out using
an internal oscillator. The OE nCS, and DCLKpins supply the control signals for the
,
address counter and the DATAoutput tri-state buffer. The configuration device sends a
serial bitstream of configuration data to its DATApin, which is routed to the DATA0
input of the FPGA.
The control signals for configuration devices, OE, nCS, and DCLK, interface directly with
the FPGA control signals, nSTATUS CONF DONE, and DCLK. All Altera FPGAs can be
,
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configured by a configuration device without requiring an external intelligent
controller.
1
An EPC2 device cannot configure FLEX 8000 or FLEX 6000 devices. For configuration
devices that support FLEX 8000 or FLEX 6000 devices, refer to Table 2.
Figure 2 shows the basic configuration interface connections between the
configuration device and the Altera FPGA.
Figure 2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device (1)
V
V
V
CC
CC
CC
Configuration
Device
(3)
(2)
(3)
FPGA
DCLK
DATA
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
nSTATUS
CONF_DONE
nCONFIG
N.C.
nCASC
n
MSEL
nCEO
nCE
N.C.
GND
Notes to Figure 2:
(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.
(2) The nINIT CONFpin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT CONF/nCONFIGline. The nINIT CONFpin does not need to be connected if its functionality is not used.
If the nINIT CONFpin is not used or unavailable, nCONFIGmust be pulled to VCC either directly or through a resistor.
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(3) EPC2devices have internal programmable pull-up resistors on OEand nCSpins. If internal pull-up resistors are used, donot use external pull-up
resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check
the Disable nCS and OE pull-ups on configuration device option when you generate programming files.
The EPC2 device allows you to begin configuration of the FPGA using an additional
pin, nINIT
nCONFIGpin of the FPGA, which allows the INIT
FPGA configuration. The INIT CONFJTAG instruction causes the EPC2 device to drive
the nINIT CONFpin low, which in turn pulls the nCONFIGpin low. Pulling the nCONFIG
pin low on the FPGA will reset the device. When the JTAG state machine exits this
state, the nINIT CONFpin is released and pulled high by an internal 1-k resistor,
which in turn pulls the nCONFIGpin high to begin configuration. If you do not use the
nINIT CONFpin, disconnect the nINIT CONFpin, and pull the nCONFIGpin of the FPGA
to VCC either directly or through a resistor.
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CONF. The nINIT
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CONFpin of the EPC2 device can be connected to the
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CONFJTAG instruction to begin
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Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
