Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 22. I/O Timing—DDR SDRAM T , T , and T
SK SA
HA
SK (ns)
T
TSA (ns)
THA (ns)
Signal Name
Minimum
Maximum
Minimum
Minimum
MemAddr00:14
BA0:2
BankSel0:1
MemClkEn
CAS
0.20
0.20
+2.3
+2.3
RAS
WE
Table 23. I/O Timing—DDR SDRAM Write TimingT and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD − 1.25 + 0.25TCYC).
TSD (ns)
THD (ns)
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM4
Reference Signal
DQS0
0.84
0.84
0.84
0.84
0.84
1.15
1.15
1.15
1.15
1.15
DQS1
DQS2
DQS3
DQS4
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC405EX can delay with very fine granularity the DQS through register programming.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data is stored in the eight Flip Flops of the Stage 1, such that it can be transferred later within a 8x period.
AMCC Proprietary
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
