AMD
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
Other enhancements to improve the Am85C30 inter-
face capabilities include:
■ A 10 × 19 bit SDLC/HDLC frame status FIFO array
■ A 14-bit SDLC/HDLC frame byte counter
■ Write data valid setup time to falling edge of WR
requirement eliminated
■ Reduced INT response time
■ Automatic SDLC/HDLC opening frame flag
transmission
■ Reduced access recovery time (tRC) to 3 PCLK
best case (3 1/2 PCLK worst case)
■ TxD pin forced High in SDLC NRZI mode after
closing flag
■ Improved Wait timing
■ Automatic SDLC/HDLC Tx underrun/EOM flag
■ Write Registers WR3, WR4, WR5, and WR10
reset
made readable
■ Automatic SDLC/HDLC Tx CRC generator reset/
■ Lower priority interrupt masking without INTACK
■ Complete SDLC/HDLC CRC character reception
preset
■ RTS synchronization to closing SDLC/HDLC flag
DTR/REQ deactivation delay significantly reduced
■ External PCLK to RxC or TxC synchronization
requirement eliminated for PCLK divide-by-four
operation
BLOCK DIAGRAM
TxDA
Baud
Rate
Generator
RxDA
Transmitter
Receiver
RTxCA
TRxCA
10×19 Bit
Frame
Status
FIFO
Internal
Control
Logic
Channel
A
Registers
DTR/REQA
SYNCA
W/REQA
RTSA
Control
Logic
Data
8
5
CPU
Bus VO
Channel A
Internal Bus
CTSA
Control
DCDA
Channel
B
Registers
TxDB
RxDB
RTxCB
TRxCB
Interrupt
Control
Logic
Interrupt
Control Lines
DTR/REQB
Channel B
SYNCB
W/REQB
RTSB
+5 V GND PCLK
CTSB
DCDB
10216F-1
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Am85C30
AMD [ AMD ]
