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AM27C256-120DC PDF Datasheet浏览和下载

型号:
AM27C256-120DC
PDF下载:
下载PDF文件
内容描述:
256千位(是32K ×8位)的CMOS易宝
[256 Kilobit (32 K x 8-Bit) CMOS EPRO]
文件大小:
164 K
文件页数:
12 Pages
品牌Logo:
品牌名称:
AMD [ ADVANCED MICRO DEVICES ]
供应:
AM27C256-120DC货源
  • 供货商
  • IC型号
  • 厂家
  • 批号
  • 数量
  • 封装
  • 单价/备注
  • 操作
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FINAL
Am27C256
256 Kilobit (32 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s
Fast access time
— Speed options as fast as 45 ns
s
Low power consumption
— 20 µA typical CMOS standby current
s
JEDEC-approved pinout
s
Single +5 V power supply
s
±10%
power supply tolerance standard
s
100% Flashrite™ programming
— Typical programming time of 4 seconds
s
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
s
High noise immunity
s
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
s
Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C256 is a 256-Kbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 32K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 4 seconds.
BLOCK DIAGRAM
V
CC
V
SS
V
PP
OE#
CE#
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
A0–A14
Address
Inputs
Output
Buffers
Data Outputs
DQ0–DQ7
Y
Gating
X
Decoder
262,144
Bit Cell
Matrix
08007I-1
Publication#
08007
Rev:
I
Issue Date:
May 1998
Amendment/0