AD6315
1/4- to 1/12 Duty VFD Controller/Driver
Pin Descriptions
Symbol
D
IN
D
OUT
Name
Data input
Data output
No.
7
6
Description
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the
shift clock, starting from low order bit. This is
N-ch open-drain output pin.
Initializes serial interface at the rising or
falling edge of the AD6315. It then waits for
reception of a command. Data input after
STB falling is processed as a command.
While command data is processed, current
processing is stopped, and the serial
interface is initialized. While STB is high, CLK
is ignored.
Reads serial data at the rising edge, and
outputs data at the falling edge.
Connect resistor in between this pin and Vss to set
up the oscillation frequency.
STB
Strobe
9
CLK
OSC
Seg
1
/KS
1
to
Seg
16
/KS
16
Grid
1
to Grid
4
Seg
17
/Grid
12
to
Seg
24
/Grid
5
LED
1
to LED
4
KEY
1
, KEY
2
V
DD
V
SS
V
EE
Clock input
Oscillator pin
High-voltage output (Segment)
High-voltage output (Grid)
High-voltage output
(Segment/grid)
LED output
Key data input
Logic power
Logic ground
Pull-down level
8
5
14 to 29
Segment output pins (Dual function as key
source)
39 to 42 Grid output pins
These pins are selectable for segment or grid
31 to 38
driving.
1 to 4
10, 11
13, 43
12, 44
30
CMOS output
Data input to these pins is latched at the end
of the display cycle.
Logic power supply
Connect this pin to system GND.
Driver power supply
Ordering Information
AD6315X X X
Package
Q: QFP-44L
L : LQFP-44L
Lead
Blank: Normal
F: Lead Free
Packing
Blank : Tray
Anachip Corp.
www.anachip.com.tw
2/16
Rev. A5 Dec 29, 2003
ANACHIP [ ANACHIP CORP ]
