AAT2833/34
240mA Total Display Solution
for Portable Devices
Functional Block Diagram
C1+ C1–
C2+ C2–
OUT
IN
Tri-Mode Charge
Pump Control
V
F
Monitoring
3
6
PGND
BL1
EN/SET
AS
2
Cwire
Control
Main Ref
BL2
BL3
BL4
Sub Ref
BL5
BL6
BSET
DAC
R
RGB Ref
G
B
AGND
Functional Description
The AAT2833/34 is a multi-functional power solu-
tion for display systems in portable devices. It
includes six individual channels for backlight white
LEDs, and three individual channels for RGB LEDs.
All of these functionalities are powered by a highly
efficient tri-mode charge pump power engine that is
capable of delivering 240mA of output current.
The six backlight channels can be turned on or off
all together, in two groups, or individually. The two-
group operation allows LEDs to be turned on and
off in for dual display applications: the main display
(BL1-BL4) and sub-display (B5-B6). The individual
on/off feature supports applications other than
main/sub-display backlighting, such as keypad
lighting. The maximum backlight current is pro-
grammable with an external resistor, R
BSET
.
The RGB channels can be programmed with up to
4096 or 64 different combinations of colors and light-
ing intensities (brightness). R, G, and B channels
are individually controlled and can be used for alter-
native functions, such as keyboard lighting, "fun"
lighting, etc.
AS
2
Cwire Serial Interface
Each current channel input on the AAT2833/34 is
controlled by AnalogicTech's AS
2
Cwire serial digital
interface. The AS
2
Cwire interface uses the number
of rising edges on the EN/SET pin to address and
load the LED configuration registers. AS
2
Cwire
latches data or addresses after the EN/SET pin has
been held logic high for longer than T
LAT
(500µs).
Addresses and data are differentiated by the num-
ber of EN/SET rising edges. Since the data registers
are 4 bits each, the differentiating number of pulses
is 2
4
or 16, so that Address 0 is signified by 17 rising
edges, Address 1 by 18 rising edges, Address 2 by
19 rising edges, and so on. Data is set to any num-
ber of rising edges between 1 and including 16.
A typical write protocol consist of the following: first
a burst of EN/SET rising edges that identify/target a
particular address followed by EN/SET being held
logic high for the T
LAT
timeout period to latch the
address value in the registers, then another burst of
rising edges that signify data with the accompanying
T
LAT
timeout period to latch the data value in the reg-
isters. Once an address is set, then multiple writes
to the corresponding data register are allowed with-
out having to write to the address for every change
9
2833.2007.09.1.0
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
