APA2058
Pin Description
PIN
I/O/P
I
FUNCTION
The inverting input pin of right channel power amplifier.
The non-inverting input pin of right channel power amplifier.
The non-inverting input pin of left channel power amplifier.
The inverting input pin of left channel power amplifier.
Power amplifier’s ground
NO.
NAME
1
RINN_A
2
3
RINP_A
LINP_A
LINN_A
PGND
LOUTP
LOUTN
PVDD
NC
I
I
4
I
5,21
6
P
O
O
P
-
The positive output pin of left channel power amplifier.
The negative output pin of left channel power amplifier.
Power amplifier’s supply voltage pin.
7
8,18
9
No Connection.
10
11
12
13
14
15
16
17
19
20
22
23
24
25
26
27
28
29
30
31
32
CPP
I/O
P
I/O
O
P
O
O
P
O
O
I
Charge pump flying capacitor positive connection.
Charge pump’s ground.
CGND
CPN
Charge pump flying capacitor negative connection.
Charge pump output pin, connect this pin to the “HVSS”.
Headphone driver’s negative supply voltage pin.
The output pin of right channel headphone driver.
The output pin of left channel headphone driver.
Headphone driver’s positive supply voltage pin.
The negative output pin of right channel power amplifier.
The positive output pin of right channel power amplifier.
Headphone drivers enable input pin; High=Enable.
Power amplifiers enable input pin; Low=Enable.
Bias voltage for power amplifiers.
CVSS
HVSS
HP_RO
HP_LO
HVDD
ROUTN
ROUTP
HP_EN
AMP_EN
I
BIAS
LDO_EN
RIN_H
LIN_H
GND
P
I
LDO (Low Drop-Out Regulator) enables input pin; High=Enable.
The input pin of right channel headphone driver.
The input pin of left channel headphone driver.
Control block’s ground, connect this pin to CGND and PGND.
LDO (Low Drop-Out Regulator)’s output pin.
Control block and LDO supply voltage pin.
I
I
P
O
P
I
LDOUT
VDD
GAIN0
GAIN1
Control pin for internal gain setting, MSB, Bit 1.
Control pin for internal gain setting, LSB, Bit 0.
I
Copyright ã ANPEC Electronics Corp.
7
www.anpec.com.tw
Rev. A.3 - Aug., 2008
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
