iPEM
4.8 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR264M72PBG1
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
VDD
V
L
VDDDD
Q
t
1
VTD
TT1
V
V
REF
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tc0
Td0
Tb0
T0
Ta0
t
CK
CK#
CK
t
t
CL
CL
SSTL_18
LVCMOS
2
2
LOW LEVEL
CKE
ODT
3
LOW LEVEL
16
7
5
6
8
9
10
REF
11
12
13
LM
4
Comman d
REF
Valid
LM
PRE
LM
LM
LM
PRE
LM
LM
NOP
15
DM
3
Address
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
15
High-Z
High-Z
High-Z
DQS
15
DQ
RTT
t
t
t
t
t
t
t
t
t
MRD
t
t
T = 400ns
16
T = 200µs (MIN)
Power-up:
RPA
MRD
MRD
MRD
MRD
RPA
RFC
RFC
MRD
MRD
(MIN)
See note 17
VDD and stable
EMR(2)
EMR(3)
EMR
MR without
EMR with
EMR with
OCD exit
clock (CK, CK#)
DLL RESET OCD default
Normal
operation
200 cycles of CK are require d before a READ comman d can be issued.
MR with
DLL RESET
Indicates a break in
time scale
Don’t care
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR264M72PBG1
Rev. 3.0 6/09
5
AUSTIN [ AUSTIN SEMICONDUCTOR ]
