IF
B
A
D.U.T.
+5 V
VCC
R
L
RM
V
O
V
FF
GND
SINGLE CHANNEL OR
COMMON VCC DEVICES
V
CM
+
-
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
V
5 V
CC
Logic Family
LSTTL
54LS14
5 V
CMOS
220 Ω
R
L
D.U.T.
Device No.
CD40106BM
V
CC
V
CC
5 V
8.ꢀ kW
15 V
TTL
R 5% Tolerance
L
18 kW *
ꢀꢀ kW
LOGIC GATE
0.01 µF
GND
EACH CHANNEL
*The equivalent output load resistance is affected by the LSTTL input
current and is approximately 8.2 kΩ. This is a worst case design
which takes into account 25% degradation of CTR. See App. Note
1002 to assess actual degradation and lifetime.
Figure 11. Recommended Logic Interface.
VCC
VOC
D.U.T.*
VCC
(EACH INPUT)
0.1 µF
+
-
VO
VIN
(EACH OUTPUT)
GND
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 µA
NOTE: BASE LEAD NOT CONNECTED.
T
= +125 ˚C
A
Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All
Channels Tested Simultaneously.
1ꢀ
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
