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HCNW2201 参数 Datasheet PDF下载

HCNW2201图片预览
型号: HCNW2201
PDF下载: 下载PDF文件 查看货源
内容描述: 非常高CMR ,宽VCC逻辑门光电耦合器 [Very High CMR, Wide VCC Logic Gate Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 18 页 / 389 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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Package Characteristics
Parameter
Input-Output Momentary
Withstand
HCNW22XX
Voltage
*
Input-Output Resistance
HCNW22XX
Input-Output Capacitance
HCNW22XX
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
I
I-I
R
I-I
C
I-I
C
I-O
Sym.
V
ISO
Min.
3750
5000
Typ.
Max.
Units
V rms
Test Conditions
RH < 50%, t = 1 min.
T
A
= 25°C
Fig.
Note
5, 10
5, 11
R
I-O
10
12
10
11
10
12
10
13
0.6
0.5
0.005
10
11
0.25
0.6
Ω
T
A
= 25°C
T
A
= 100°C
pF
V
I-O
= 500 Vdc
5
f = 1 MHz,
T
A
= 25°C, V
I-O
= 0 Vdc
5
12
12
12
µA
Relative Humidity = 45%,
t = 5 s, V
I-I
= 500 V
Ω
pF
V
I-I
= 500 V
f = 1 MHz
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203
Notes:
1. Each channel.
2. Derate total package power dissipation, P
T
, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
3. Duration of output short circuit time should not exceed 10 ms.
4. For single devices, input capacitance is measured between pin 2 and pin 3.
5. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
6. The t
PLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of
the output pulse. The t
PHL
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the
trailing edge of the output pulse.
7. CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V
O
> 2.0 V.
CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V
O
< 0.8 V.
8. For HCPL-2202/12, V
O
is on pin 6.
9. Use of a 0.1
µF
bypass capacitor connected between pins 5 and 8 is recommended.
10. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for one second (leakage
detection current limit, I
I-O
≤5
µA).
This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for one second (leakage
detection current limit, I
I-O
≤5
µA).
This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-2 Insulation Characteristics Table.
12. For HCPL-2231/32 only. Measured between pins 1 and 2, shorted together, and pins 3 and 4, shorted together.
13