Package Characteristics
All Typicals at T
A
= 25˚C.
Parameter
Sym.
Package
Input-Output
Insulation
Input-Output
Momentary
Withstand
Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation
Leakage
Current
Resistance
(Input-Input)
Capacitance
(Input-Input)
I
I-O
*
V
ISO
Single 8-Pin DIP
Single SO-8
8-Pin DIP, SO-8
Min.
Typ.
Max
1
Units
µA
V rms
Test Conditions
45% RH, t = 5 s,
V
I-O
= 3 kV DC, T
A
= 25˚C
RH ≤ 50%, t = 1 min,
T
A
= 25˚C
Fig.
Note
16, 17
16, 17
3750
R
I-O
C
I-O
I
I-I
8-Pin, SO-8
8-Pin DIP, SO-8
Dual Channel
10
12
0.6
0.005
Ω
pF
µA
V
I-O
=500 V dc
f = 1 MHz, T
A
= 25˚C
RH ≤ 45%, t = 5 s,
V
I-I
= 500 V
1, 16, 19
1, 16, 19
20
R
I-I
C
I-I
Dual Channel
Dual 8-Pin Dip
Dual SO-8
10
11
0.03
0.25
Ω
pG
f = 1 MHz
20
20
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip-
ment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The t
PLH
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
7. The t
PHL
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
8. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature and specified test
conditions.
9. See test circuit for measurement details.
10. The t
ELH
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The t
EHL
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. CM
H
is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., V
o
> 2.0 V).
13. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., V
o
< 0.8 V).
14. For sinusoidal voltages, (|dV
CM
| / dt)
max
= πf
CM
V
CM
(p-p).
15. No external pull up is required for a high logic state on the enable input. If the V
E
pin is not used, tying V
E
to V
CC
will result in improved
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage
detection current limit, I
I-O
≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, I
I-O
≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/
EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
12
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
