欢迎访问ic37.com |
会员登录 免费注册
发布采购

HCPL-0721-500E 参数 Datasheet PDF下载

HCPL-0721-500E图片预览
型号: HCPL-0721-500E
PDF下载: 下载PDF文件 查看货源
内容描述: 40 ns的传播延迟, CMOS光电耦合器 [40 ns Propagation Delay, CMOS Optocoupler]
分类和应用: 光电输出元件
文件页数/大小: 18 页 / 292 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
 浏览型号HCPL-0721-500E的Datasheet PDF文件第2页浏览型号HCPL-0721-500E的Datasheet PDF文件第3页浏览型号HCPL-0721-500E的Datasheet PDF文件第4页浏览型号HCPL-0721-500E的Datasheet PDF文件第5页浏览型号HCPL-0721-500E的Datasheet PDF文件第6页浏览型号HCPL-0721-500E的Datasheet PDF文件第7页浏览型号HCPL-0721-500E的Datasheet PDF文件第8页浏览型号HCPL-0721-500E的Datasheet PDF文件第9页  
HCPL-0720, HCPL-7720, HCPL-0721 and HCPL-7721
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-772X/072X require only two bypass ca-
pacitors for complete CMOS compatability.
Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor-
porates an integrated photodiode, a high-speed tran-
simpedance amplifier, and a voltage comparator with an
output driver.
Features
+5 V CMOS compatibility
20 ns maximum prop. delay skew
High speed: 25 MBd
40 ns max. prop. delay
10 kV/µs minimum common mode rejection
–40 to 85°C temperature range
Safety and regulatory approvals
UL recognized
– 3750 V
rms
for 1 min. per UL 1577
– 5000 V
rms
for 1 min. per UL 1577
(for HCPL-772X option 020)
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– V
IORM
= 630 V
peak
for HCPL-772X option 060
– V
IORM
= 567 V
peak
for HCPL-072X option 060
Functional Diagram
**V
DD1
V
I
1
8
V
DD2
**
NC*
TRUTH TABLE
(POSITIVE LOGIC)
V
I
, INPUT
H
L
LED1
O
2
I
O
LED1
7
fieldbus
OFF
Digital
H
ON
bus, SDS
L
Applications
V , OUTPUT
isolation: CC-Link, DeviceNet, Profi-
*
3
6
V
O
GND
1
4
SHIELD
5
GND
2
AC plasma display panel level shifting
Multiplexed data transmission
Computer peripheral interface
Microprocessor system interface
Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed data sheet performance. Pin 7 is not connected
internally.
** A 0.1
µF
bypass capacitor must be connected between pins 1 and
4, and 5 and 8.
*
TRUTH TABLE
POSITIVE LOGIC
V
I
H
L
LED1
OFF
ON
V
o
OUTPUT
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.