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HCPL-0723-500E 参数 Datasheet PDF下载

HCPL-0723-500E图片预览
型号: HCPL-0723-500E
PDF下载: 下载PDF文件 查看货源
内容描述: 50 MBd的2纳秒PWD高速CMOS光电耦合器 [50 MBd 2 ns PWD High Speed CMOS Optocoupler]
分类和应用: 光电输出元件
文件页数/大小: 12 页 / 196 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either 8-pin DIP or SO-8 package style respec-
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve outstanding
speed performance of minimum 50 MBd data rate and
2 ns maximum pulse width distortion.
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals:
UL recognized
– 5000 V
rms
for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 V
rms
for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– V
iorm
= 630 V
peak
for HCPL-7723 option 060
– V
iorm
= 567 V
peak
for HCPL-0723 option 060
Functional Diagram
**V
DD1
V
I
1
8
V
DD2
**
NC*
2
I
O
LED1
7
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
NC*
3
6
V
O
GND
1
4
SHIELD
5
GND
2
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
V
I
, INPUT
H
L
LED1
OFF
ON
V
O
, OUTPUT
H
L
CAUTION:
It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.