Package Characteristics
All Typicals at T = 25°C.
A
Parameter
Sym.
Package
Min.
Typ.
Max.
Units
Test Conditions
45% RH, t = 5 s,
I-O = 3 kV dc, T = 25°C
Fig.
Note
Input-Output
Insulation
II-O*
VISO
Single 8-Pin DIP
Single SO-8
1
A
20, 21
V
A
Input-Output
Momentary With-
stand Voltage**
8-Pin DIP, SO-8
Widebody
OPT 020†
3750
5000
5000
V rms RH ≤ 50%, t = 1 min,
20, 21
20, 22
T = 25°C
A
Input-Output
Resistance
RI-O
8-Pin DIP, SO-8
Widebody
1012
1013
VI-O = 500 V dc
1, 20,
23
1012
1011
T = 25°C
A
T = 100°C
A
Input-Output
Capacitance
CI-O
II-I
8-Pin DIP, SO-8
Widebody
0.6
0.5
pF
f = 1 MHz, T = 25°C
1, 20,
23
A
0.6
Input-Input
Insulation
Dual Channel
0.005
A
RH ≤ 45%, t = 5 s,
24
V = 500 V
I-I
Leakage Current
Resistance
(Input-Input)
RI-I
CI-I
Dual Channel
1011
24
24
Capacitance
(Input-Input)
Dual 8-Pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. Avago specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous volt-
age rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment
level safety specification or Avago Application Note 1074 entitled“Optocoupler Input-Output Endurance Voltage.”
†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 μA. Avago guarantees a maximum IOH of 100 A.
7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. Avago guarantees a maximum ICCH of 10 mA.
8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. Avago guarantees a maximum ICCL of 13 mA.
9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. Avago guarantees a maximum IEL of -1.6 mA.
10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the
output pulse.
11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the
output pulse.
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions.
13. See application section titled“Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew”for more information.
14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge
of the output pulse.
15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge
of the output pulse.
16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V).
17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V).
18. For sinusoidal voltages, (|dVCM | / dt)max = fCMVCM(p-p).
19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR
performance. For single channel products only.
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for one second (leakage detection
current limit, II-O ≤ 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
5-2 Insulation Characteristics Table, if applicable.
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second (leakage detection
current limit, II-O ≤ 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-
5-2 Insulation Characteristics Table, if applicable.
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only
14
AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
