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HCPL-7710 参数 Datasheet PDF下载

HCPL-7710图片预览
型号: HCPL-7710
PDF下载: 下载PDF文件 查看货源
内容描述: 40 ns的传播延迟, CMOS光耦合器8 ns的最大脉冲宽度失真 [40 ns Propagation Delay, CMOS Optocoupler 8 ns maximum pulse width distortion]
分类和应用: 光电脉冲输出元件
文件页数/大小: 17 页 / 332 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstand-
ing performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC, which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimpedance
amplifier, and a voltage comparator with an output driver.
Functional Diagram
**V
DD1
V
I
1
8
V
DD2
**
NC*
Features
+5 V CMOS compatibility
8 ns maximum pulse width distortion
20 ns maximum prop. delay skew
High speed: 12 Mbd
40 ns maximum prop. delay
10 kV/µs minimum common mode rejection
-40°C to 100°C temperature range
Safety and regulatory approvals
UL Recognized
3750 V
rms
for 1 min. per UL 1577
5000 V
rms
for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-5
– V
IORM
=
TRUTH TABLE
630 V
peak
for HCPL-7710 Option 060
(POSITIVE LOGIC)
V
peak
for HCPL-0710 Option 060
– V
IORM
= 567
LED1
V
O
, OUTPUT
OFF
H
Applications
ON
L
Digital fieldbus isolation: DeviceNet, SDS, Profibus
AC plasma display panel level shifting
Multiplexed data transmission
Computer peripheral interface
Microprocessor system interface
V
I
, INPUT
H
L
2
I
O
LED1
7
NC*
3
6
V
O
GND
1
4
SHIELD
5
GND
2
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
8
V
DD2
**
NC*
TRUTH TABLE
(POSITIVE LOGIC)
V
I
, INPUT
H
L
LED1
OFF
ON
V
O
, OUTPUT
H
L
7
I
O
6
V
O
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
5
GND
2