THEORY OF OPERATION
The ADS7844 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µs CMOS process.
The basic operation of the ADS7844 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+V
CC
. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7844.
The analog input to the converter is differential and is
provided via an eight-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configura-
tion is selectable via the digital interface.
A2
0
1
0
1
0
1
0
1
A1
0
0
0
0
1
1
1
1
A0
0
0
1
1
0
0
1
1
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
+IN
+IN
+IN
+IN
+IN
+IN
+IN
+IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS7844. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The voltage on the
–IN input is limited between –0.2V and 1.25V, allowing the
input to reject small signals which are common to both the
+IN and –IN input. The +IN input has a range of –0.2V to
+V
CC
+ 0.2V.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
CH0
+IN
CH1
–IN
CH2
CH3
CH4
CH5
CH6
CH7
+IN
–IN
+IN
–IN
+IN
–IN
–IN
+IN
–IN
+IN
–IN
+IN
–IN
+IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
TABLE II. Differential Channel Control (SGL/DIF LOW).
+2.7V to +5V
ADS7844
1
2
Single-ended
or differential
analog inputs
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
+V
CC
20
D
CLK
19
CS 18
D
IN
17
BUSY 16
D
OUT
15
GND 14
GND 13
+V
CC
12
V
REF
11
0.1µF
1µF to 10µF
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
10 SHDN
1µF to 10µF
FIGURE 1. Basic Operation of the ADS7844.
®
9
ADS7844
BURR-BROWN [ BURR-BROWN CORPORATION ]
