DIGITAL OPERATION
SYSTEM CONFIGURATION
The DAC1220 is controlled by 8-bit instruction codes (INSR)
and 16-bit command codes (CMR) via the serial interface,
which is externally clocked.
The DAC1220 Microcontroller (MC) consists of an ALU
and a register bank. The MC has three states: power-on reset,
calibration, and normal operation. In the power-on reset
state, the MC resets all the registers to their default states. In
the calibration state, the MC performs offset and gain self-
calibration. In the normal state, the MC performs D/A
conversions.
The DAC1220 has five internal registers, as shown in
Table II. Two of these, the Instruction Register (INSR) and
the Command Register (CMR), control the operation of the
converter. The Instruction register utilizes an 8-bit instruc-
tion code to control the serial interface to determine whether
the next operation is either a read or a write, to control the
word length and to select the appropriate register to
read/write. Communication with the DAC1220 is controlled
via the INSR. The INSR is written as the first part of each
serial communication. The instruction that is sent determines
what type of communication will occur next. It is not
possible to read the INSR. The Command register has a 16-
bit command code to set up the DAC1220 operation mode,
resolution mode, settling mode and data format. The Data
Input Register (DIR) contains the value for the next conver-
sion. The Offset and Full-Scale Calibration Registers (OCR
and FCR) contain data used for correcting the internal
conversion value after it is placed into the DIR. The data in
these two registers may be the result of a calibration routine,
or they may be values which have been written directly via
the serial interface.
INSR
DIR
CMR
OCR
FCR
Instruction Register
Data Input Register
Command Register
Offset Calibration Register
Full-Scale Calibration Register
8 Bits
24 Bits
16 Bits
24 Bits
24 Bits
R/W (Read/Write) Bit—For
a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
R/W
0
1
Write
Read
MB1, MB0 (Multiple Bytes) Bits—These
two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
MB1
0
0
1
MB0
0
1
0
1 Byte
2 Bytes
3 Bytes
A3 – A0 (Address) Bits—These
four bits select the begin-
ning register location that will be read from or written to, as
shown in Table III. Each subsequent byte will be read from
or written to the next higher location (increment address).
If the BD bit in the Command register is set, each subse-
quent byte will be read from or written to the next lower
location (decrement address). This bit does not affect INSR
register or the write operation for the CMR register. If the
next location is reserved in Table III, the results are un-
known. Reading or writing continues until the number of
bytes specified by MB1 and MB0 have been transferred.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Input Register Byte 2 MSB
Data Input Register Byte 1
Data Input Register Byte 0 LSB
Reserved
Command Register Byte 1 MSB
Command Register Byte 0 LSB
Reserved
Reserved
Offset Cal Register Byte 2 MSB
Offset Cal Register Byte 1
Offset Cal Register Byte 0 LSB
Reserved
Full-Scale Cal Register Byte 2 MSB
Full-Scale Cal Register Byte 1
Full-Scale Cal Register Byte 0 LSB
Reserved
TABLE II. DAC1220 Registers.
Instruction Register (INSR)
Each serial communication starts with the 8 bits of the INSR
being sent to the DAC1220. The read/write bit, the number
of bytes n, and the starting register address are defined, as
shown in Table III. When the n bytes have been transferred,
the instruction is complete. A new communication cycle is
initiated by sending a new INSR (under restrictions outlined
in the Interfacing section).
MSB
R/W
MB1
MB0
0
A3
A3
A1
LSB
A0
TABLE IV. A3 - A0 Addressing.
TABLE III. Instruction Register.
®
7
BURR-BROWN [ BURR-BROWN CORPORATION ]
