A1
L
(1)
L
H
H
X
(2)
X
A0
L
H
L
H
X
X
LOADDACS
L
L
L
L
H
X
RESET
H
H
H
H
H
L
SELECTED
DAC
REGISTER
A
B
C
D
NONE
ALL
STATE OF
SELECTED
DAC
REGISTER
Transparent
Transparent
Transparent
Transparent
(All Latched)
Reset
(3)
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7614 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong DAC.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
Digital Input Coding
NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or
800
H
, per the RESETSEL state (LOW = 000
H
, HIGH = 800
H
). When RESET
rises, all registers that are in their latched state retain the reset value.
TABLE II. Control Logic Truth Table.
CS
(1)
H
(2)
L
(4)
L
↑
H
(6)
H
(6)
CLK
(1)
X
(3)
L
↑
(5)
L
X
X
LOADDACS
H
H
H
H
L
(7)
H
RESET
H
H
H
H
H
L
(8)
SERIAL SHIFT REGISTER
No Change
No Change
Advanced One Bit
Advanced One Bit
No Change
No Change
The DAC7614 input data is in Straight Binary format. The
output voltage is given by the following equation:
V
OUT
= V
REFL
+
(V
REFH
– V
REFL
) • N
4096
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADDACS is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
TABLE III. Serial Shift Register Truth Table.
®
11
DAC7614
BURR-BROWN [ BURR-BROWN CORPORATION ]
