This expression indicates that, in general, there is a correlation
between the THD and the square root of the sum of the squares
of the linearity errors at each digital word of interest. How-
ever, this expression does not mean that the worst-case linear-
ity error of the D/A is directly correlated to THD.
For PCM67 and PCM69A the test period is set at an 8X
oversampling rate (352.8kHz = 44.1kHz
•
8), which is the
typical sample rate for CD player applications.
The test signal frequency is 991Hz and the amplitude of the
signal level is F/S (0dB), and –60dB down from F/S.
All THD tests are performed without a deglitcher circuit and
without a 20kHz low pass filter.
SYSTEM CLOCK REQUIREMENTS
The PCM67 and PCM69A need a system clock for the one-bit
noise shaping DAC operation.
The PCM67 is capable of only a 384Fs corollary system clock
frequency such as 192Fs, 96Fs (24 times word rate or integer
multiple of 24).
The PCM69A is capable of any system clock up from 48Fs to
384Fs such as 384Fs, 256Fs, 100Fs with condition for timing
as described in “Timing of PCM69A” in Figure 5.
The user can choose either model for their application.
Table II shows the different SYSCLK options.
The PCM67/69A accepts TTL compatible logic input levels.
The data format of the PCM67/69A is BTC with the most
significant bit (MSB) being first in the serial input bit stream.
t
SL
t
SH
SYS Clock
t
DH
Data
LSB
t
DSU
Bit Clock
t
CH
WD Clock
t
CL
t
CW
t
WC
t
DHO
t
WH
t
WL
t
SH
:
t
SL
:
t
DW
:
t
DSU
:
t
DHO
:
t
CH
:
t
CL
:
t
CW
:
t
WC
:
t
WH
:
t
WL
:
SYS Clock High Pulse Width : 15ns, min
SYS Clock Low Pulse Width : 15ns, min
Data Valid Time : 20ns, min
Data Setup Time : 10ns, min
Data Hold Time : 5ns, min
Bit Clock High Pulse Width : 15ns, min
Bit Clock Low Pulse Width : 15ns, min
WD Clock Fall Time From Bit Clock Rise : 10ns, min
Bit Clock Rise Time From WD Clock Fall : 15ns, min
WD Clock High Pulse Width : 1 SYS Clock Cycle, min
WD Clock Low Pulse Width : 1 SYS Clock Cycle, min
MODEL
PCM67
PCM69A
BASIC SYSCLK
384Fs
OTHER CAPABLE
SYSCLK
192Fs, 96Fs
FIGURE 4. Timing Specification.
TIMING OF PCM69A
PCM69A timing is similar to PCM67 except that PCM69A is
capable of operating from any system clock up to 384Fs. For
synchronized operation, PCM69A system clock and WDCK
timing must be as shown in Figure 5.
Any Clock (with timing condition)
Examples: 384Fs, 300Fs, 256Fs, 200Fs, 90Fs
TABLE II. System Clock Requirements.
LOGIC TIMING
The serial data bit transfers are triggered on positive bit clock
(BCK) edges. The serial-to-parallel data transfer to the DAC
occurs on the falling edge of Word Clock (WDCK). The
change in the output of the DAC coincides with the falling
edge of WDCK.
Refer to Figure 3 for graphical relationships of these signals.
The setup and hold timing relationships for these signals are
shown in Figure 4.
WDCK
t
n1
SYSCLK
t
n2
SYSCLK
R-ch Data
L-ch Data
Bit Clock
WD Clock
SYS Clock
MSB
bit2
bit17 LSB MSB bit2
bit17 LSB
t
n1
: WDCK Fall Delay From Rise of SYSCLK : min 10ns
t
n2
: SYSCLK Rise Delay From Fall of WDCK : min 20ns
MSB
bit2
bit17 LSB MSB bit2
bit17 LSB
FIGURE 5. Timing of PCM69A for SYSCLK and WDCK.
1 WDCK
FIGURE 3. Timing Diagram.
®
7
PCM67/69A
BURR-BROWN [ BURR-BROWN CORPORATION ]
