8. Consider PC board layout which minimizes parasitic
capacitance, especially in high gain.
SELECTING R
S
R
SPAN
is chosen to that a given full scale input span e
INFS
will result in the desired full scale output span of
∆I
OFS
,
[(0.016
) + (40/R
S
)]
∆e
IN
=
∆I
O
= 16mA.
40
∆I
O
/∆e
IN
– 0.016
Solving for R
S
:
Ω
R
S
=
(1)
Ω
Figure 6 shows a similar connection for a resistive trans-
ducer. The transducer could be excited either by one (as
shown) or both current sources. Also, the offset adjustment
has higher resolution compared to Figure 5.
CMV AND CMR
The XTR101 is designed to operate with a nominal 5V
common-mode voltage at the input and will function prop-
erly with either input operating over the range of 4V to 6V
with respect to pin 7. The error caused by the 5V CMV is
already included in the accuracy specifications.
If the inputs are biased at some other CMV then an input
offset error term is (CMV – 5)/CMRR; CMR is in dB,
CMRR is in V/V.
SIGNAL SUPPRESSION AND ELEVATION
In some applications it is desired to have suppressed zero
range (input signal elevation) or elevated zero range (input
signal suppression). This is easily accomplished with the
XTR101 by using the current sources to create the suppres-
sion/elevation voltage. The basic concept is shown in Fig-
ures 7 and 8(a). In this example the sensor voltage is derived
from R
T
(a thermistor, RTD, or other variable resistance
element) excited by one of the 1mA current sources. The
other current source is used to create the elevated zero range
voltage. Figures 8(b), (c) and (d) show some of the possible
circuit variations. These circuits have the desirable feature
of noninteractive span and suppression/elevation adjust-
ments. Note: It is not recommended to use the optional offset
voltage null (pins 1, 2 and 14) for elevation/suppression.
This trim capability is used only to null the amplifier’s input
offset voltage. In many applications the already low offset
voltage (typically 20µV) will not need to be nulled at all.
Adjusting the offset voltage to nonzero values will disturb
the voltage drift by
±0.3µV/°C
per 100µV or induced offset.
For example, if
∆e
INFS
= 100mV for
∆I
OFS
= 16mA,
R
S
=
40
40
=
16mA/100mV) – 0.016
0.16 – 0.016
40
= 278Ω
0.144
=
See Typical Performance Curves for a plot of R
S
vs
∆e
INFS
.
Note that in order not to exceed the 20mA upper range limit,
e
IN
must be less than 1V when R
S
=
∞
and proportionately
smaller as R
S
decreases.
BIASING THE INPUTS
Because the XTR operates from a single supply both e
1
and
e
2
must be biased approximately 5V above the voltage at pin
7 to assure linear response. This is easily done by using one
or both current sources and an external resistor R
2
. Figure 5
shows the simplest case— a floating voltage source e'
2
. The
2mA from the current sources flows through the 2.5kΩ
value of R
2
and both e
1
and e
2
are raised by the required 5V
with respect to pin 7. For linear operation the constraint is
+4V
≤
e
1
≤
+6V
+4V
≤
e
2
≤
+6V
The offset adjustment is used to remove the offset voltage of
the input amplifier. When the input differential voltage (e
IN
)
equals zero, adjust for 4mA output.
e
1
3
1mA
1mA
5
+
e
IN
–
R
S
6
11
–
10
8
D
1
11
e
1
3
5
–
2mA
e
IN
+
e
2
4
+
e'
2
R
S
Adj.
6
XTR101
–
10
8
D
1
XTR101
0.01µF
+ 24V +
e
L
– R
L
–
4-20 mA
4
0.01µF
+ 24V +
e
L
– R
L
–
+
e
2
–
R
T
e
2
2 14
100kΩ
1
1MΩ
R
2
2.5kΩ
2mA
+5V
0.01µF
+
7
Offset
Adjust
+
1 1MΩ
2
14
7
I
O
Offset
Adjust
I
O
= 4mA + (0.016
0.01µF
R
2
2.5kΩ
2mA
+5V
Alternate circuitry
shown in Figure 8.
+ 40 )e
IN
R
S
e
IN
= e'
2
= 1mA
X
R
T
I
O
= 4mA + (0.016
e
IN
= e
2
+ 40 )e
IN
R
S
FIGURE 6. Basic Connection for Resistive Source.
FIGURE 5. Basic Connection for Floating Voltage Source.
®
XTR101
8
Ω
Ω
BURR-BROWN [ BURR-BROWN CORPORATION ]
