Shanghai Belling Corp., Ltd
Figure 3.
Output Acknowledge
BL24C32/64
3.
Device Addressing
The 32K/64K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 4).
The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits
as shown. This is common to all the Serial EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the
same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0
pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to
float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip
will return to a standby state.
NOISE PROTECTION:
Special internal circuitry placed on the SDA and SCL pins prevent small noise
spikes from activating the device.
DATA SECURITY:
The 24C32/24C64 has a hardware data protection scheme that allows the user to
write protect the entire memory when the WP pin is at VCC.
4.
Write Operations
BYTE WRITE:
A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, t
WR
, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the write is
complete (see Figure 5).
5
BELLING [ SHANGHAI BELLING CO., LTD. ]
