BSI
n
DATA RETENTION CHARACTERISTICS (T
A
= -25 C to +85 C)
SYMBOL
V
DR
I
CCDR
(3)
BH616UV8010
O
O
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.0V
V
CC
=2.0V
MIN.
1.0
--
0
TYP.
(1)
--
0.5
2.5
--
--
MAX.
--
3.0
12
--
--
UNITS
V
uA
ns
ns
t
CDR
t
R
See Retention Waveform
t
RC (2)
1. T
A
=25
O
C.
2. t
RC
= Read Cycle Time.
3. I
CCDR(MAX.)
is 2.5uA /10uA at V
CC
=1.0V/2.0V and T
A
=0
O
C ~ 70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.0V
V
CC
t
CDR
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.0V
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ1
, t
CLZ2
, t
BE
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
BDO
, t
OHZ
, t
WHZ
, t
OW
Output Load
Others
V
CC
/ 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
ALL INPUT PULSES
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV8010
4
Revision 1.0
Jul.
2005
BSI [ BRILLIANCE SEMICONDUCTOR ]
