Very Low Power CMOS SRAM
128K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV2019
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 3.6V
Ÿ
Very low power consumption :
V
CC
= 3.0V
Operation current : 25mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.3uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns(Max.) at V
CC
=2.7~3.6V
-70
70ns(Max.) at V
CC
=2.4~3.6V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
Ÿ
I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS616LV2019 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.3uA at 3.0V/25
O
C and maximum access time of 55ns at
2.7V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS616LV2019DC
BS616LV2019AC
BS616LV2019TC
BS616LV2019AI
BS616LV2019TI
Industrial
-40
O
C to +85
O
C
5.0uA
2mA
10mA
25mA
Commercial
+0
O
C to +70
O
C
3.0uA
1.5mA
9mA
23mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
f
Max.
V
CC
=3.0V
1MHz
V
CC
=3.0V
10MHz
DICE
BGA-48-0608
TSOP I-48
BGA-48-0608
TSOP I-48
n
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0
n
BLOCK DIAGRAM
BS616LV2019TC
BS616LV2019TI
A6
A7
A8
A9
A10
A11
A15
A14
A13
A12
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
.
.
.
.
.
.
DQ15
16
.
.
.
.
.
.
Data
Input
Buffer
16
128
Column Decoder
7
Control
Address Input Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
NC
2
OE
UB
D10
D11
D12
D13
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
NC
D0
D2
VCC
VSS
D6
D7
NC
V
CC
V
SS
CE2,CE
WE
OE
UB
LB
A16 A0
A1
A2
A3
A4
A5
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS616LV2019
1
Revision 1.3
May.
2006
BSI [ BRILLIANCE SEMICONDUCTOR ]
