BSI
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
Data Retention Mode
BS616LV4010
V
DR
≥
1.5V
Vcc
V
IH
Vcc
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
1V/ns
0.5Vcc
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
1269
Ω
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1269
Ω
3.3V
OUTPUT
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
5PF
1404
Ω
INCLUDING
JIG AND
SCOPE
,
1404
Ω
FIGURE 1A
THEVENIN EQUIVALENT
667
Ω
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 70ns
MIN. TYP. MAX.
CYCLE TIME : 100ns
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
70
--
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
--
--
35
35
30
--
100
--
--
--
--
15
15
15
--
--
--
15
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
--
--
40
40
35
--
NOTE :
1. t
BA
is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; t
BA
is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616LV4010
4
Revision 2.4
Jan.
2004
BSI [ BRILLIANCE SEMICONDUCTOR ]
