B SI
FEATURES
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
DESCRIPTION
BS616LV2013
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V
C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2013DC
BS616LV2013EC
BS616LV2013TC
BS616LV2013AC
BS616LV2013DI
BS616LV2013EI
BS616LV2013TI
BS616LV2013AI
OPERATING
TEMPERATURE
Vcc
RANGE
The BS616LV2013 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2013 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2013 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
SPEED
( ns )
Vcc=3.0V
( I
CCSB1
, Max )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=3.0V
PKG TYPE
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
+0
O
C to +70
O
C
2.4V ~3.6V
70/100
0.7uA
20mA
-40
O
C to +85
O
C
2.4V ~ 3.6V
70/100
1.5uA
25mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
BS616LV2013EC
BS616LV2013EI
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
OE
UB
D10
D11
D12
D13
A0
A3
A5
N.C.
N.C.
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
N.C.
D0
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE
D1
D3
D4
D5
WE
A11
CE
D2
VCC
VSS
Vcc
Gnd
WE
OE
UB
LB
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
D14
D15
N.C.
D6
D7
N.C.
N.C.
A8
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV2013
48-ball BGA top view
1
Revision 2.5
April 2002
BSI [ BRILLIANCE SEMICONDUCTOR ]
