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BS616LV1015ECP55 参数 Datasheet PDF下载

BS616LV1015ECP55图片预览
型号: BS616LV1015ECP55
PDF下载: 下载PDF文件 查看货源
内容描述: 非常低的功率/电压CMOS SRAM 64K ×16位 [Very Low Power/Voltage CMOS SRAM 64K X 16 bit]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 255 K
品牌: BSI [ BRILLIANCE SEMICONDUCTOR ]
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BSI
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV1015
Vcc
V
IH
Vcc
V
DR
1.5V
Vcc
t
CDR
CE
Vcc - 0.2V
t
R
V
IH
CE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc/0V
1V/ns
0.5Vcc
C
L
=30pF+1TTL
C
L
=100pF+1TTL
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
,
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C, Vcc = 5.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
E1LQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
E1HQZ
t
BDO
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
55
--
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
--
--
--
10
10
10
--
--
--
5
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
35
35
--
--
--
35
35
30
--
R0201-BS616LV1015
4
Revision 1.1
Jan.
2004