Data Sheet
Electrical Characteristics
(T
J
= T
C
= T
A
= +25°C , V
EE
= -5.2V, V
RB
= -2.0V, V
RM
= -1.0V, V
RT
= 0.00V, ƒ
CLK
= 750MHz, Duty Cycle=50%,
unless otherwise specified)
cDK1302a
symbol
parameter
Resolution
cDl1302B
Max
Min
typ
8
+1.0
+0.95
-1.5
-0.95
+1.5
+1.5
Guaranteed
V
RT
V
RB
0.75
15
15
900
500
+30
+30
-30
-30
5
2
60
80
30
750
+30
+30
V
RT
2.0
V
mA
kΩ
pF
MHz
MHz
mV
mV
V/ns
μA
Ω
MHz
MHz
2
250
1.9
2.25
0.9
1.25
44
42
-43
-35
44
36
41
34
1.4
1.75
1.9
2.25
ps
ps
ns
ns
dB
dB
dBc
dBc
dB
dB
dB
dB
conditions
Min
typ
8
Max
units
CDK1302
8-bit, 750 MSPS, Flash A/D Converter
bits
LSB
LSB
DC Performance
DLE
ILE
Differential Linearity Error
(1)
Integral Linearity Error
No Missing Codes
(1)
ƒ
clk
= 100MHz
ƒ
clk
= 100MHz
-1.0
-0.85
Guaranteed
V
RB
Analog Input
Input Voltage Range
(1)
Input Bias Current
(1)
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
Large Signal
Offset Error
(2)
Offset Error
(2)
V
IN
= 0V
Over Full Input Range
0.75
15
15
900
500
2.0
V
RT
V
RB
-30
-30
5
2
60
80
30
750
2
250
Input Slew Rate
Clock Synchronous Input Currents
Reference Input
Ladder Resistance
(1)
Reference Bandwidth
Timing Characteristics
Maximum Sample Rate
(1)
Aperture Jitter
Acquisition Time
CLK to Data Delay
(2)
REV 1A
0.9
1.25
ƒ
IN
= 50MHz
(1)
ƒ
IN
= 250MHz
(1)
ƒ
IN
= 50MHz
(1)
ƒ
IN
= 250MHz
(1)
ƒ
IN
= 50MHz
(1)
ƒ
IN
= 250MHz
(1)
1.4
1.75
CLK to Data Ready Delay
(2)
Dynamic Performance
SNR
THD
SFDR
SINAD
notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
3. Typical Thermal Impedance:
θ
JC
= +4°C/W.
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
46
44
-45
-37
48
40
43
36
ƒ
IN
= 50MHz
(1)
ƒ
IN
= 250MHz
(1)
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
