Data Sheet
Pin Configuration
QFN-64, TQFP-64
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1
2
3
4
5
6
7
8
9
10
11
12
DVSSCLK
DVDDCLK
CLKP
CLKN
49
48
47
46
45
44
QFN-64, TQFP-64
CDK2307
43
42
41
40
39
38
37
36
35
34
33
CLK_EXT
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Assignments
Pin No.
1, 18, 23
2
3, 9, 12
4, 5, 8
6, 7
10, 11
13
14
15
16
17, 64
19
20
21
22
24, 41, 58
25, 40, 57
26
27
28
29
Pin Name
DVDD
CM_EXT
AVDD
AVSS
IP0, IN0
IP1, IN1
DVSSCLK
DVDDCLK
CLKP
CLKN
DVSS
CLK_EXT_EN
DFRMT
PD_N
OE_N_1
OVDD
OVSS
D1_0
D1_1
D1_2
D1_3
Description
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog ground
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground
Digital circuitry ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,
always apply Power Down mode before using Active Mode to reset chip.
Output Enable Channel 0. Tristate when high.
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
Output Data Channel 1 (LSB, 13-bit output or 1V
pp
full scale range )
Output Data Channel 1 (LSB, 12-bit output 2V
pp
full scale range)
Output Data Channel 1
Output Data Channel 1
CLK_EXT_EN
Rev 2B
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
