CM3131
Functional Description
The CM3131-01 / -11 and CM3131-02 provide
power for DDR-I/DDR-II memories from three
voltage regulators on-chip with either one or two
external N-FETs respectively. There is an over-
temperature thermal shutdown if any of the
regulators overheat. Each regulator has reverse
current protection in the event of any being shut
down.
The linear regulator-driver/s with external N-FET/s
can provide up to 15A at 2.5V/1.8V for the V
DDQ
of
DDR-I/-II memory, from an input supply voltage of
2.8V-3.6V. An external feedback resistor divider,
connected to the SENSE1 pin, enables selection of
V
DDQ
output voltages from 2.2V to 2.8V for use with
DDR-I memories requiring other than 2.5V for V
DDQ
.
V
DDQ
= 1.25V x (R1+R2)/R2. When SENSE1 is
connected to GND or left open, V
DDQ
is fixed at
2.50V (and VTT at 1.25V). For DDR-II operation,
V
DDQ
can be set from 1.7V to 1.9V.
The V
TT
regulator is a linear source-sink regulator
powered from the V
DDQ
output that supplies the V
TT
supply required by DDR-I memory termination
resistors. This regulator sinks or sources up to 2A at
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V
CC
PSOP-8
CM3131-01/11
1.25V to or from the DDR-I bus termination resistors.
For DDR-II applications, the regulator sinks or
sources 0.65A at 0.9V. The V
TT
output voltage
accurately tracks V
DDQ
/2 to 1%. When there is no
V
CC
provided, V
TT
is powered down and its output is
0V. This regulator has overload current limiting of
2.5A.
The standby regulator is a LDO regulator that is
powered from a standby voltage, V
STBY
, of 3.3V or
5V, and supplies a regulated output of up to 500mA
to the V
DDQ
of the DDR memory to enable it to retain
its contents during the standby mode. It provides
2.5V for DDR-I and 1.8V for DDR-II.
The CM3131-01 and CM3131-11 differ with regards
the selection of truth table for determining which S0-
S5 sequencing matrix the chip is set for. The
CM3131-02 has both EN and SEL pins to more
accurately define each Sx stage without monitoring
the V
CC
or V
STBY
voltages.
Two CM3131s can be ganged together to provide
V
DDQ
power to dual channels of DDR memory, and
the memory controller chip of any chip set.
V
DDQ
LDO Drive
DRIVE
Internal V
SBY
voltage
doubler ensures V
G
> 5.3V
Drives any N-FET with C
GS
<1200pF
FET
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V
CC
CM3131-02
DRIVE1
V
DDQ
LDO Drives
DRIVE2
5V
STBY
/ 3.3V
STBY
V
DDQ1
V
DDQ
LDOs
V
DDQ
/ V
TT
Control
V
DDQ
C
SBY
C
CC
Linear
Source-Sink
V
TT
Reg
GND
V
DDQ2
N-FET1
N-FET2
5V
STBY
/ 3.3V
STBY
V
DDQ
LDO
V
DDQ
/ V
TT
Control
V
DDQ
V
DDQ
R1
V
DDQ
V
DDQ1
V
DDQ2
R1
C
DDQ2
R3
SEL / EN
SEL
SENSE
R2
GND
V
TT
C
TT
C
DDQ
C
SBY
C
CC
Linear
Source-Sink
V
TT
Reg
GND
V
TT
Only needed for
DDR-I if V
DDQ
is
not 2.5V, e.g. 2.6V
or 2.7V.
Set to 1.7V to
1.9V for DDR-II
SENSE1
SENSE2
R2
EN
R4
GND
C
DDQ1
V
TT
C
TT
V
TT
Examples of Single and Dual N-FET Drive Configurations
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
