®
®
ADCDS-1403
POWER REQUIREMENTS
Power Supply Current
+12V Supply
Power Supply Current
+5V Supply
–5V Supply
Power Dissipation
Power Supply Rejection
(5%) @ +25°C
ENVIRONMENTAL
Operating Temperature Range
ADCDS-1403
ADCDS-1403EX
Storage Temperature
Package Type
Weight
MIN.
TYP.
MAX.
UNITS
initial offset and gain errors can be reduced to zero using the
FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2)
features.
Direct Mode (AC Coupled)
—
—
—
—
—
+13
+40
–27
0.50
±0.02
+16
+46
–35
0.60
±0.03
mA
mA
mA
Watts
%
FSR/
%
V
This is the most common input configuration as it allows the
ADCDS-1403 to interface directly to the output of the CCD with
a minimum amount of analog "front-end" circuitry. This mode
of operation is used with full-scale video input signals from
0.350Vp-p to 2.8Vp-p.
Figure 2a. describes the typical configuration for applications
using a video input signal with a maximum amplitude of
0.350Vp-p. The coarse gain of the input amplifier is
determined from the following equation:
V
OUT
= 2.8Vp-p = V
IN
*(1+(523/75)), with all internal resistors
having a 1% tolerance. Additional fine gain adjustment can be
accomplished using the Fine Gain Adjust (pin 1 see Figure 5).
Figure 2b. describes the typical configuration for applications
using a video input signal with an amplitude greater than
0.350Vp-p and less than 2.8Vp-p. Using a single external
series resistor (see Figure 4.), the coarse gain of the ADCDS-
1403 can be set, with additional fine gain adjustments being
made using the Fine Gain Adjust function (pin 1 see Figure 5).
The coarse gain of the input amplifier can be determined from
the following equation:
V
OUT
= 2.8Vp-p = V
IN
*(1+(523/(75+Rext))), with all internal
resistors having a 1% tolerance.
4
759
5239
0
–55
–65
—
—
—
+70
+125
+150
°C
°C
°C
40-pin, TDIP
16.10 grams
TECHNICAL NOTES
1. Obtaining fully specified performance from the
ADCDS-1403 requires careful attention to pc-card layout
and power supply decoupling. The device's analog and
digital grounds are connected to each other internally.
Depending on the level of digital switching noise in the
overall CCD system, the performance of the ADCDS-1403
may be improved by connecting all ground pins
(7,32,33,35, 37) to a large
analog
ground plane beneath
the package. The use of a single +5V
analog
supply for
both the +5V
A
(pin 36) and +5V
D
(pin 34) may also be
beneficial.
2. Bypass all power supplies to ground with a 4.7µf tantalum
capacitor in parallel with a 0.1µf ceramic capacitor. Locate
the capacitors as close to the package as possible.
3. If using the suggested offset and gain adjust circuits
(Figure 3 & 5), place them as close to the ADCDS-1403's
package as possible.
4. A0 and A1 (pins 30, 31) should be bypassed with 0.1µf
capacitors to ground to reduce susceptibility to noise.
ADCDS-1403 Modes of Operation
The input amplifier stage of the ADCDS-1403 provides the
designer with a tremendous amount of flexibility. The
architecture of the ADCDS-1403 allows its input-amplifier to
be configured in any of the following configurations:
·
Direct Mode (AC coupled)
·
Non-Inverting Mode
·
Inverting Mode
When applying inputs which are less than 2.8Vp-p, a coarse
gain adjustment (applying an external resistor to pin 4) must
be performed to ensure that the full scale video input signal
(saturated signal) produces a 2.8Vp-p signal at the input-
amplifier's output (V
out
).
In all three modes of operation, the video portion of the signal
at the CDS input (i.e. input-amplifier's V
out
) must be more
negative than its associated reference level and V
out
should
not exceed ±2.8V DC.
The ADCDS-1403 achieves it specified accuracies without the
need for external calibration. If required, the device's small
V
IN
NO CONNECT
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2a.
Rext
4
759
5239
V
IN
NO CONNECT
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2b.
Rext
759
5239
4
NO CONNECT
V
IN
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2c.
3
CANDD [ C&D TECHNOLOGIES ]
