24LC08
8K-Bit Serial EEPROM
FUNCTION DESCRIPTION
I C-BUS INTERFACE
2
The 24LC08 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of
a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to
V
CC
by a pull-up resistor that is located somewhere on the bus.
2
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to two 24LC08 devices can be
2
connected to the same I C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter
or receiver, but the master device determines which bus operating mode would be active.
V
CC
V
CC
R
R
SDA
SCL
Slave 1
Bus Master
(Transmitter/
Receiver)
MCU
To V
CC
or V
SS
To V
CC
or V
SS
24LC08
Tx/Rx
A0 A1 A2
Slave 2
24LC08
Tx/Rx
A0 A1 A2
NOTES:
1.
The A0, A1 do not affect the device address of the 24LC08.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I
2
C-Bus)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
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of 23
Rev 1.1 Nov.18, 2002
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