CS4202
3.1
AC-Link Serial Data Output Frame
In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4202 from the AC ’97
controller. Figure 9 illustrates the serial port timing.
The PCM playback data being passed to the CS4202 is shifted out MSB first in the most significant bits
of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in
its corresponding slot and dithered or zero-padded in the unused bit positions.
Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.
3.1.1
Serial Data Output Slot Tags (Slot 0)
2
Res
1
0
Codec Codec
ID1
ID0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
Valid Slot 1 Slot 2 Slot 3 Slot 4
Not
Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12
Frame Valid Valid Valid Valid Implem Valid Valid Valid Valid Valid Valid Valid
Valid Frame
The Valid Frame bit determines if any of the following slots contain either valid playback data
for the CS4202 or data for read/write operations. When ‘set’, at least one of the other AC-link
slots contains valid data. If this bit is ‘clear’, the remainder of the frame is ignored.
The Slot 1 Valid bit indicates a valid register read/write address for a primary codec.
The Slot 2 Valid bit indicates valid register write data for a primary codec.
The Slot [3:4,6:11] Valid bits indicate the validity of data in their corresponding serial data out-
put slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’,
the corresponding slot will be ignored.
The Slot 12 Valid bit indicates if output Slot 12 contains valid GPIO control data.
The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link
frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01,
10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID
value of 01, 10, or 11 also indicates a valid read/write address and/or valid register write data
for a secondary codec.
Slot 1 Valid
Slot 2 Valid
Slot [3:4,6:11] Valid
Slot 12 Valid
Codec ID[1:0]
3.1.2
Bit 19
R/W
Command Address Port (Slot 1)
18
RI6
17
RI5
16
RI4
15
RI3
14
RI2
13
RI1
12
RI0
11
10
9
8
7
6
5
Reserved
4
3
2
1
0
R/W
Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index
bits will occur in the AC ’97 2.x audio codec. When the bit is ‘cleared’, a write will occur. For
any read or write access to occur, the Valid Frame bit (F0) must be ‘set’ and the Codec ID[1:0]
bits (F[14:15]) must match the Codec ID of the AC ’97 2.x audio codec being accessed. Ad-
ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and
both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For
a secondary codec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’
for read and write accesses. See Figure 9 for bit frame positions.
Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the
CS4202. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’
to access CS4202 registers.
DS549PP2
RI[6:0]
16
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